ICFPT 05 » Keynotes

IEEE 2005 Conference on
Field-Programmable Technology (FPT)
http://www.icfpt.org/

Venue: Kent Ridge Guild House,
National University of Singapore
Singapore
December 11-14, 2005

Co-sponsorship by

IEEE Circuit and Systems Society
IEEE Singapore Section

School of Computing, National University of Singapore

Technical Co-sponsorship by

Electron Devices Society, IEEE

Invited Keynote Speeches

First Keynote

Platform-Based Synthesis for Field-Programmable SOCs

Speaker: Jason Cong, UCLA

Latest FPGAs offer a rich platform as field-programmable system-on-chips (FP-SOCs), including a variety of field-programmable components for system-level implementation, including hard and soft processors, , a large amount of field-programmable logic, and various kinds of embedded memories, IP blocks, and programmable I/Os. Such FP-SOCs offer great potential for rapid system prototyping and implementation, but also presents significant challenge to the synthesis capability of existing EDA tools in terms of making efficient use of system-level components and architectures in the FP-SOCs. In this talk, I shall present the platform-based synthesis system, named xPilot, being developed at UCLA. The first objective of xPilot is to provide novel behavioral synthesis capability for generating efficient RTL code from C or System-C description automatically for a given FPGA platform for logic, interconnects, performance, and power optimization. The second objective of xPilot is to provide platform-based system-level synthesis capability for automatic generation of software for embedded processors, RTL description for programmable logic, and associated interface logic. In particular, xPilot can synthesize application-specific instruction-set processors through automatic identification and implementation of extensible instructions of field-programmable processors. Preliminary experiments of xPilot on two FP-SOC platforms demonstrate the efficacy of our approach on a number of applications and its value in exploring various kinds of design tradeoffs for behavior-level or system-level designs.

About the Speaker

Jason Cong received his B.S. degree in computer science from Peking University in 1985, his M.S. and Ph. D. degrees in computer science from the University of Illinois at Urbana-Champaign in 1987 and 1990, respectively. Currently, he is a Professor and Chairman of the Computer Science Department of University of California, Los Angeles, and co-director of the VLSI CAD Laboratory. His research interests include synthesis and layout of VLSI circuits, highly scalable VLSI design algorithms and tools, design and synthesis of programmable circuits and systems, system-on-a-chip designs, and computer architectures. He has published over 220 research papers and led over 30 research projects supported by DARPA, NSF, SRC, and a number of industrial sponsors in these areas. He served on technical program committees and executive committees of many professional conferences, such as DAC, ICCAD, and ISCAS, including serving as the General Chair of the 1993 ACM/SIGDA Physical Design Workshop, the Program Chair and General Chair of the 1997 and 1998 Int'l Symp. on FPGAs, respectively, the Program Co-Chair of the 1999 Int'l Symp. on Low-Power Electronics and Designs, and the Program Co-Chair and General Co-Chair of ASPDAC'2003 and ASPDAC’2005, respectively. He served as an Associate Editor for IEEE Trans. on VLSI Systems from 1999 to 2002, and has been an Associate Editor of ACM Trans. on Design Automation of Electronic Systems since 1995. He served on the ACM SIGDA Advisory Board from 1993 – 1999. He served on the Board of Governors of the IEEE Circuits and Systems Society during 2001 - 2004. Dr. Cong received the Best Graduate Award from the Peking University in 1985, and the Ross J. Martin Award for Excellence in Research from the University of Illinois at Urbana-Champaign in 1989. He received the NSF Young Investigator Award in 1993, the Northrop Outstanding Junior Faculty Research Award from UCLA in 1993, and the ACM/SIGDA Meritorious Service Award in 1998. He has received three best paper awards, including the 1995 IEEE Trans. on CAD Best Paper Award, the 2005 International Symposium on Physical Design Best Paper Award, and the 2005 ACM Transaction on Design Automation of Electronic Systems Best Paper Award. He also received the SRC Inventor Recognition Award and the SRC Technical Excellence Award both in 2000. He was elected to an IEEE Fellow in 2000. Dr. Cong has served or is serving on the Technical Advisory Board of a number of EDA and silicon IP companies, including Atrenta, eASIC, FlexChip, Get2Chip, Kilopass Technologies, Magma Design Automation, and Ultima Interconnect Technologies. He was the founder and president of Aplus Design Technologies, Inc., until it was acquired by Magma Design Automation in 2003. Currently, he serves as the Chief Technologist Advisor of Magma. He is also a Guest Professor of Peking University since 2000.
 

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Second Keynote

Low Power and High Speed Issues in FPGA Chips

Speaker: Tadao Nakamura, Tohoku University

In the era of digital multimedia, we have a large variety of chips for functions in many applications. Full custom chips and ASICs are popular in industry due to very low prices for high volume production. On the other hand, FPGAs are approaching commercial viability on larger and larger volumes, even though they have shortcomings in speed, power and area (cost). The features of FPGAs are in some sense outstanding in terms of rapidly building up functional chips minimizing development time and therefore giving us a shortcut in the development of chips. Thinking of FPGA Technology, the issue of low power and high speed requires us to consider the whole system in terms of both hardware and software. In particular, power consumption of FPGAs includes a high price for gate-level reconfigurability. This talk will discuss low power issues with FPGAs within a whole system, based on the concept of efficiency in energy.


About the speaker

Tadao Nakamura received his PhD in Electronics using Computer Aided Design in 1972 from Tohoku University. Dr. Nakamura is currently a Professor of the Department of Computer and Mathematical Sciences at Tohoku University. He was founding chair of the department in 1993. Prior to that he was a Professor of the Department of Mechanical (Machine Intelligence and Systems) Engineering at Tohoku University and a Visiting Lecturer in the Department of Information Science at the University of Tokyo. From 1994-98 he was a Visiting Professor of Electrical Engineering at Stanford University. His recent research interests are in computer architecture, especially pipelining based microarchitecture, and low power concepts in chips, in general. He was elected in 2004 to receive the IEEE Computer Society Taylor L. Booth Award. He has been Organizing Committee Chair of the COOL Chips conference series fully sponsored by the IEEE Computer Society. Dr. Nakamura was elected Fellow of the IEEE in 2002 for contributions to pipelined computer architecture and computer engineering education.