Reading List for CS5271         

The following is a sample reading list to give an impression of what will be covered in this course.

  1. S. Chakraborty et al.: “Performance evaluation of network processor architectures: combining simulation with analytical estimation”, Computer Networks, 41(5):641—665, April 2003
     

  2. S. Chakraborty, S. Künzli and L. Thiele: “A general framework for analysing system properties in platform-based embedded system designs”, In Proc. 6th Design, Automation and Test in Europe (DATE), Germany, March 2003
     

  3. K. Richter et al.: “Bottom-up performance analysis of HW/SW platforms”, In Proc. Distributed and Parallel Embedded Systems Workshop (DIPES), Canada, 2002
     

  4. K. Richter, M. Jersak and R. Ernst: “A formal approach to MpSoC performance verification”, IEEE Computer, 36(4):60—67, 2003
     

  5. Y-T. S. Li, S. Malik and A. Wolfe: “Performance estimation of embedded software with instruction cache modeling”, ACM Transactions on Design Automation of Electronic Systems, 4(3):257—279, 1999
     

  6. H. Theiling, C. Ferdinand and R. Wilhelm: “Fast and precise WCET prediction by separated cache and path analysis”, Real-Time Systems, 18(2/3):157—179, 2000
     

  7. X. Li, T. Mitra and A. Roychoudhury: “Accurate timing analysis by modeling caches, speculation and their interaction”, In Proc. 40th ACM Design Automation Conference (DAC), USA, 2003
     

  8. S. Chakraborty et al.: “Scheduling event-driven code blocks in real-time embedded systems”, In Proc. 39th ACM Design Automation Conference (DAC), USA, 2002
     

  9. K. Lahiri, A. Raghunathan and S. Dey: “System-level performance analysis for designing on-chip communication architectures”, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 20(6):768—783, 2001
     

  10. T-Y. Yen and W. Wolf: “Performance evaluation of real-time distributed embedded systems”, IEEE Trans. on Parallel and Distributed Systems, 9(11):1125—1136, 1998
     

  11. P. Pop, P. Eles and Z. Peng: “Performance estimation for embedded systems with data and control dependencies”, In Proc. 8th Intl. Symp. on Hardware/Software Codesign (CODES), 2000
     

  12. M.A. Franklin and T. Wolf: “A network processor performance and design model with benchmark parameterization”, In Network Processor Design: Issues and Practices, vol. 1, chap. 6, pages 117—140, 2003
     

  13. L. Thiele et al.: “Design space exploration of network processor architectures”, In Network Processor Design: Issues and Practices, vol. 1, chap. 4, pages 55—90, 2003
     

  14. W. Fornaciari et al.: “A sensitivity-based design space exploration methodology for embedded systems”, Design Automation for Embedded Systems, 7(1-2), 2002
     

  15. A.D. Pimentel et al.: “Exploring embedded systems architectures with Artemis”, IEEE Computer, 34(11):57—63, 2001

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