Copyright Notice:
The papers listed below are solely intended for students of CS5271. The ps/pdf
files of these papers are being provided with purely academic intentions. Please
note that all of these papers have been published and their copyrights are owned
by the respective publishers. Therefore, these papers cannot be duplicated for
commercial purposes. The following is ACM's
copyright notice; other publishers have similar ones.
Copyright © 199x by the Association for Computing Machinery, Inc. Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that new copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted.
Here you will find a list of suggested project proposals. These projects should ideally be done in groups of two. However, you are also free to do a project alone. The proposals given below are merely suggestions. You are most welcome to do a project based on your own idea. The projects can be implementation oriented, or can be more theoretical in nature, or can be a critical survey. As a rough estimate and guide, your final report should be around 15 - 20 pages when typeset in this format (Latex).
Please discuss your project proposal with the course instructor before you start working. Please keep the course instructor regularly informed about your progress and meet him whenever you need help. The submission deadline will be announced later and will be somewhere near the end of the semester. We will have a brief presentation (approx 20 mins) of each project towards the end of the semester (before the submission of the project report). Please decide on your project as soon as possible.
Note: The papers listed below may be downloaded from the publishers' website using the NUS digital library. Because of copyright issues the pdf files cannot be made available here.
|
Topic |
Description |
| Survey of Performance Analysis Techniques for Network Processors | Network Processors are specialized processors targeted
specifically towards network packet processing. They are mostly built into
network routers and switches, to perform complicated packet processing tasks
(e.g. forwarding, encryption/decryption, transcoding) at high line speeds.
Typically Network Processors are heterogeneous multiprocessors and consist of a mix of fully programmable, partially programmable and fixed
function processor cores. Of late, there has been a lot of activity in the area of developing different models and methods for the performance analysis of such network processors - which involve specific techniques applicable only in the context of network processor like architectures. The goal of this project is to do a critical survey of this area - compare the different techniques, and discuss their relative advantages and disadvantages. A major emphasis should be on tools available for network processor performance evaluation. The survey should NOT merely list a set of papers and their abstracts. References: (This is just a partial list of papers to help you to get started. You should find more papers on your own.)
|
| Survey of Design Space Exploration Techniques: Tool Oriented Approach | The problem of designing the hardware-software architecture
of an embedded system involves the process of enumerating all possible
architectures (i.e. which the architectural components to be chosen, how
they should be interconnected, the software architecture of the application,
and the mapping of the application onto the architecture), evaluating them,
and finally choosing the "optimal" architecture. This process of enumerating
all possible solutions or the walk in the architectural design space, is
called "design space exploration". Note that this problem is very closely
related to the problem of "evaluating" any potential solution/architecture.
The goal of this survey would be to critically compare the different known techniques for design space exploration in the context of embedded systems. Again, we would NOT like to have a "list" of known techniques, but YOUR views on which techniques you think might be good and why, and what are their advantages over other techniques, and discussions along those lines. The survey should be focused towards tools and implementation - which methods do you think would be feasible to implement in a tool, what kinds of tools are already existing, how do you think that they can be improved, and related discussions. Additionally, you are required to download one or two publicly available toolsets for design space exploration, install them and perform a small case study. The case study should involve designing a small problem and using the tool you installed to solve the problem i.e. exploring the design space underlying the problem and identifying the optimal architecture. As a starting point, you may refer to the following recent survey:
The above survey should provide you a relatively exhaustive list of references and tools. Your survey should contain YOUR opinion about these papers and tools. One possible tool you can use for the case study is given below. You are free to use additional/other tools. |
| Survey of Generalized Event Models and Associated Scheduling Techniques | The system-level view of multiprocessor system-on-chip
architectures that was presented in the class is the following. An
application is partitioned into several functions, which are then mapped
onto the different processors. A stream of events enter a processor and is
processed by the function that is mapped onto this processor, and the
(partially) processed stream then enters another processor for further
processing. In this context, we discussed standard event models (like
periodic, sporadic, etc.) and the relationship between their input and
output when multiple event streams are being processed by a processor
according to some specified scheduling policy. We then discussed one
particular generalized event model, how standard event models can be
represented in this model and what are the input-output relations in the
case of this generalized event model for different scheduling policies (like
fixed priority, round robin, etc.). The aim of this survey is to study other known generalized event models, analyze their expressive power and also study how they can be analyzed for different scheduling policies. As a starting point, you may look at the models described in the papers listed below. But this is by no means an exhaustive list, you are expected to do an extensive literature search and report and study other comparable models and their associated analysis techniques.
|
| Schedulability Analysis Using Timed Automata | This is a research oriented project with the aim of
developing an automata theoretic approach to represent event streams and
also processor availability (as we did using the concept of "service curves"
in the class). Based on such a representation, we would then like to
develop analysis techniques such as those for schedulability analysis. References:
|
| Implementation Oriented Projects | You may also choose to do an implementation oriented
project, in contrast to the term papers or research projects mentioned
above. Typically, such a project would be of the following form. You will
select one or more applications (say an MPEG decoder and an MP3 decoder),
partition these applications into different parts and map them onto some
target architecture. The target architecture would most likely be
constituted by multiple processors connected by some by communication
subsystem. You will then be required to simulate, profile and analyze the
resulting system and suggest an optimal architecture to support the chosen
application. Depending on how complicated the problem you have chosen is,
you might also choose to solve only a part of what is mentioned above. As an
example, you can determine the optimal partitioning and mapping of the two
decoders for two (or multiple) processors, to minimize the on-chip buffer
requirements. You might choose to use simulators/languages like SimpleScalar,
SystemC and Simics to model processors and/or the communication subsystem of
your target architecture. As a guide to the kind of applications and architectures you can choose, you may refer to the "experimental evaluation / implementation sections" of the following papers:
|