PHAN Thi Xuan Linh

Analysis of Stream Processing Systems

Recently there has been a growing interest in models and methods targeted towards the (co)design of stream processing applications; e.g. those for audio/video processing. Streams processed by such applications tend to be highly bursty and exhibit a high data-dependent variability in their processing requirements. As a result, classical event and service models such as periodic, sporadic, etc. can be overly pessimistic when dealing with such applications. In this paper, we present a new model called Event Count Automata (ECAs) for capturing the timing properties of such streams. Our model can be used to cleanly formulate properties relevant to stream processing on heterogeneous multiprocessor architectures, such as buffer overflow/underflow constraints. It can also provide the basis for developing analysis methods to compute delay/timing properties of the processed streams under different scheduling policies. Our ECAs, though similar in flavor to timed and hybrid automata, have different semantics, are more light-weight, and are specifically suited for modeling stream processing applications and architectures. We study the basic aspects of the model and illustrate its modeling potential. We then apply it in a specific stream processing setting and develop methods for analyzing the ECA model. The basic theory of ECA and its associated analysis techniques provide a more versatile and efficient methodology for analyzing stream processing systems.

Sun Zhenxin

Introduction to the Open Core Protocol (OCP)

The Open Core Protocol (OCP) standard is one of the most exciting, leading-edge technology initiatives to hit the intellectual property (IP) / system-on-chip (SoC) industry. The OCP was defined to support today's on-chip, system-level design practices, is completely bus-independent and captures all of an IP core's communication requirements. OCP will help designers released from communication design and focus on the functionality level design issues. Furthermore, OCP will enable reuse without rework, the plug and play technology will shorten the time-to-market greatly.

Liu Haibing

Automated Design of Custom Architecture for Embedded Systems

An embedded system runs one specific application throughout its lifetime. This gives designers the opportunity to develop customized processor for an embedded application. However, given the short time-to-market constraint for embedded systems, this customization should be (semi)-automatic. Currently, processor customization is performed in an ad-hoc manner. The aim of this project is to develop a systematic methodology to choose and implement performance optimal customization within area and energy constraints.

Vivy SUHENDRA

WCET-guided Scratchpad Memory Allocation

Scratchpad memory is a popular choice for on-chip storage in real-time embedded systems. Data is allocated at compile time, making memory access latencies predictable, thus allowing tighter worst-case execution time (WCET) estimation which is important for real-time systems. Current scratchpad memory allocation techniques focus on improving the average case performance. Our experiments found that average-case guided allocation does not always yield optimal performance in the worst case, which is the key concern in real-time embedded systems. In this talk, we present and evaluate several scratchpad allocation techniques that aim to minimize the WCET of the application. We will also touch briefly on the WCET estimation method employed in our allocation techniques.

YUAN Yi

Physically-Aware HW-SW Partitioning for Reconfigurable Architectures with
Partial Dynamic Reconfiguration

Many reconfigurable architectures offer partial dynamic configurability, but current system-level tools cannot guarantee feasible implementations when exploiting this feature. We present a physically aware hardware-software (HW-SW) scheme for minimizing application execution time under HW resource constraints, where the HW is a reconfigurable architecture with partial dynamic reconfiguration capability. Such architectures impose strict placement constraints that lead to implementation infeasibility of even optimal scheduling formulations that ignore the nature of these constraints. We propose an exact and a heuristic formulation that simultaneously partition, schedule, and do linear placement of tasks on such architectures. With our exact formulation, we prove the critical nature of placement constraints. We demonstrate that our heuristic generates high-quality schedules by comparing the results with the exact formulation for small tests and a popular, but placement unaware scheduling heuristic for larger tests. With a case study, we demonstrate extension of our approach to handle heterogenous architectures with specialized resources distributed between general purpose programmable logic columns. The execution time of our heuristic is very reasonable- task graphs with hundreds of nodes are processed in a couple of minutes.

Dinesh Kunchamwar

Synthesis of Multiprocessor Architectures for Multimedia

Abstract: Multimedia applications typically consist of a large number of tasks, each of which can be mapped onto a different processor on a SoC platform. This gives rise to a large design space (whose size can be exponential in the number of tasks in the application). In this work we present an efficient design space exploration method using a Branch and Bound algorithm. We show that for this class of applications it is possible to come up with efficient bounding conditions based on buffer constrains and timing constraints associated with the multimedia streams. We are currently in the process of implementing our scheme and performing a case study based on the MPEG-2 decoder application.