9am

  Andre DeHon, Caltech

  Marco Platzner, University of Paderborn

  Platform-Based Synthesis for Field-Programmable SOCs

  Jason Cong, UCLA

• A Custom Instruction Approach for Hardware and Software Implementations of Finite Field Arithmetic over F_(2^163) using Gaussian Normal Bases, M. Juliato, G. Araujo, J. López and R. Dahab (State Univ. of Campinas)

• High-Radix Systolic Modular Multiplication on Reconfigurable Hardware, C. McIvor, M. McLoone and J. V. McCanny (Queen's Univ. of Belfast)

• Pipelining Saturated Accumulation, K. Papadantonakis, N. Kapre, S. Chan and A. DeHon (Caltech)

• A Parameterized Floating-Point Exponential Function for FPGAs, J. Detrey and F. de Dinechin (ENS-Lyon)

• Increasing Flexibility in FPGA-Based Reconfigurable Platforms: The Erlangen Slot Machine, C. Bobda, M. Majer, A. Ahmadinia, T. Haller, A. Linarth and J. Teich (Univ. of Erlangen-Nürnberg)

• Task Placement for Heterogeneous Reconfigurable Architectures, M. Koester, H. Kalte and M. Porrmann (Univ. of Paderborn)

• A Framework for Dynamic Resource Assignment and Scheduling on Reconfigurable Mixed-Mode On-Chip Multiprocessors, X. Wang and S. G. Ziavras (New Jersey Inst. of Technology)

• Dynamic Loading of Peripherals on Reconfigurable System-on-Chip, Y. Lu and N. Bergmann (Univ. of Queensland)

• An FPGA Model for Developing Dynamic Circuit Computing, T. Oliver and D. Maskell (Nanyang Tech. Univ.)

• ADH: An Aspect Described Hardware Programming Language, A. Bainbridge-Smith and S-H. Park (Univ. of Canterbury)

• From TLM to FPGA: Rapid Prototyping with SystemC and Transaction Level Modeling, W. Klingauf and R. Günzel (Tech. Univ. of Braunschweig)

• Rapid Reconfiguration of an Optically Differential Reconfigurable Gate Array with Pulse Lasers, M. Miyano, M. Watanabe and F. Kobayashi (Kyushu Inst. of Tech.)

• Hardware-Accelerated SSH on Self-Reconfigurable Systems, I. Gonzalez, F. J. Gomez-Arribas and S. Lopez-Buedo (Univ. Autonoma de Madrid)

• A Fast and Efficient FPGA-based Implementation for Solving a System of Linear Interval Equations, A. Sudarsanam and D. Aravind (Utah State Univ.)

• Heuristics for Context-Caches in 2-Level Reconfigurable Architectures, S. Lange and M. Middendorf (Univ. of Leipzig)

• Performance of Sorting Algorithms on a Reconfigurable Computer, J. Harkins, T. El-Ghazawi, E. El-Araby and M. Huang (George Washington Univ)

• A Zero-Overhead Dynamic Optically Reconfigurable Gate Array, M. Watanabe and F. Kobayashi (Kyushu Inst. of Tech.)

• High Quality Uniform Random Number Generation Through LUT Optimised Linear Recurrences, D. B. Thomas and W. Luk (Imperial College)

• Solving the Minimum Dominating Set Problem with Instance-Specific Hardware on FPGAs, S. Wakabayashi and K. Kikuchi (Hiroshima City Univ.)

• Custom Hardware Architectures for Posture Analysis, M. P. T. Juvonen, J. G. F. Coutinho, J. L. Wang, B. L. Lo, W. Luk, O. Mencer and G. Z. Yang (Imperial College)

  Low Power and High Speed Issues in FPGA Chips

  Tadao Nakamura, Tohoku University

• Correlation-Based Fingerprint Matching using FPGAs, A. Lindoso, L. Entrena, C. López-Ongil and J. Liu (Univ. Carlos III of Madrid)

• A Single-Chip FPGA Implementation of Real-Time Adaptive Background Model, K. Appiah and A. Hunter (Lincoln Univ.)

• FPGA-based hardware for physical modelling sound synthesis by finite difference schemes, E. Motuk, R. Woods and S. Bilbao (Queen's Univ. of Belfast)

• Have GPUs made FPGAs redundant in the field of Video Processing?, B. Cope, P. Y. K. Cheung and W. Luk (Imperial College)

• S5: The Architecture and Development Flow of a Software Configurable Processor, J. M. Arnold (Stretch Inc.)

• RoMultiC: Fast and Simple Configuration Data Multicasting Scheme for Coarse Grain Reconfigurable Device, V. Tunbunheng, M. Suzuki and H. Amano (Keio Univ.)

• Pipeline scheduling for array based reconfigurable architectures considering interconnect delays, S. Gao, K. Seto, S. Komatsu and M. Fujita (Univ. of Tokyo)

• The Transmogrifier-4: An FPGA-Based Hardware Development System with Multi-Gigabyte Memory Capacity and High Host and Memory Bandwidth, J. Fender, J. Rose and R. Galloway (Univ. of Toronto)

• High Performance Channel Model Hardware Emulator for 802.11n, A. Dassatti, G. Masera, M. Nicola, A. Concil and A. Poloni (Politecnico di Torino)

• HW/SW Interface Synthesis based on Avalon Bus Specification for Nios-oriented SoC Design, F. Lin, H. Wang and J. Bian (Tsinghua Univ.)

• A Reconfigurable Architecture for Implementing Multiple Cipher Algorithms, A. Valizadeh, M. S. Zamani, B. Sadeghian and F. Mehdipour (Islamic Azad Univ. of Shahriar - Shahre Ghods)

• Low Latency Elliptic Curve Cryptography Accelerators for NIST Curves over Binary Fields, C. Shu, K. Gaj and T. El-Ghazawi (George Washington Univ.)

• A System-Level Design Methodology for Reconfigurable Computing Applications, E. El-Araby, T. El-Ghazawi and K. Gaj (George Washington Univ.)

• Optimal FFT Architecture Selection for OFDM Receivers on FPGA, M. Petrov and M. Glesner (Darmstadt Univ. of Tech.)

• An FPGA-Based Infant Monitoring System, P. Dickinson, K. Appiah, A. Hunter and S. Ormston (Lincoln Univ.)

• FPGA-Based Conformance Testing and System Prototyping of an MPEG-4 SA-DCT Hardware Accelerator, A. Kinane, A. Casey, V. Muresan and N. O'Connor (Dublin City Univ.)

• FPGA Core Network Modeling, Implementation and Optimization in a Heterogeneous Computing Platform: A Case Study, S. Fischaber, R. Hasson, J. McAllister and R. Woods (Queen's Univ. of Belfast)

• High-Speed Hardware Architectures of the Whirlpool Hash Function, M. McLoone, C. McIvor and A. Savage (Queen's Univ. of Belfast)

• Secure Partial Reconfiguration of FPGAs, A. S. Zeineddini and K. Gaj (George Mason Univ.)

• An Adaptive Cryptographic Accelerator for IPsec on Dynamically Reconfigurable Processor, Y. Hasegawa, S. Abe, H. Matsutani, K. Anjo, T. Awashima and H. Amano (Keio Univ.)

• Dynamic Voltage Scaling for Commercial FPGAs, C. T. Chow, L. S. M. Tsui, P. H. W. Leong (Chinese Univ. of Hong Kong), W. Luk (Imperial College) and S. Wilton (Univ. of British Columbia)

• FPGA Architecture for Standby Power Management, R. P. Bharadwaj, R. Konar, D. Bhatia and P. T. Balsara (Univ. of Texas, Dallas)

• FPGA Defect Tolerance: Impact of Granularity, A. J. Yu and G. G. F. Lemieux (Univ. of British Columbia)

• A State-Serial Viterbi Decoder Architecture for Digital Radio on FPGA, M. Petrov and M. Glesner (Darmstadt Univ. of Tech.)

• A Design Methodology to Generate Dynamically Self-Reconfigurable SoCs for Virtex-II Pro FPGAs, G. Van den Branden, A. Touhafi and E. Dirkx (Eramushogeschool Brussel)

• Implementation of Gabor-type Filters on Field Programmable Gate Arrays, O. Y. H. Cheung, P. H. W. Leong, E. K. C. Tsang and B. E. Shi (Chinese Univ. of Hong Kong)

• A Scaleable FFT/IFFT Kernel for Communication Systems using Codesign Approach, P. Potipantong, T. Wiangtong, P. Sirisuk and A. Worapishet (Mahanakorn Univ. of Tech.)

• FPGA Based Router for Cognitive Packet Networks, L. A. Hey, P. Y. K. Cheung and M. Gellman (Imperial College)

• An Overview of High-Level Synthesis of Multiprocessors for Logic Programming, A. Fidjeland and W. Luk (Imperial College)

• Implementation of EAX Mode of Operation for FPGA Bitstream Encryption and Authentication, M. M. Parelkar and K. Gaj (George Mason Univ)

• Net Power directed Clustering Algorithm for Low Net-Power Implementation of FPGAs, S. Launders, W. Cooper and B. Foley (Univ. of Dublin)

• The Design of Scalable Stochastic Biochemical Simulator on FPGA, M. Yoshimi, Y. Osana, Y. Iwaoka, A. Funahashi, N. Hiroi, Y. Shibata, N. Iwanaga, H. Kitano and H. Amano (Keio Univ.)

• Designing an FPGA SoC using a Standardized IP Block Interface, L. Shannon, B. Fort, A. Patel, S. Parikh, M. Saldana and P. Chow (Univ. of Toronto)

• A Dynamically Reconfigured UMTS Multi-Channel Complex Code Matched Filter, I. O. Kennedy (Univ. of Edinburgh)

• Prototyping Automatic Cloud Cover Assessment (ACCA) Algorithm for Remote Sensing On-Board Processing on a Reconfigurable Computer, E. El-Araby, M. Taher, T. El-Ghazawi and J. Le Moigne (George Washington Univ.)

• Reconfigurable Acceleration for Monte Carlo based Financial Simulation, G. L. Zhang, P. H. W. Leong, C. H. Ho, K. H. Tsoi, C. C. C. Cheung, D-U. Lee, R. C. C. Cheung and W. Luk (Imperial College)

• Accelerating FPGA Routing Using Architecture-Adaptive A* Techniques, A. Sharma and S. Hauck (Univ. of Washington)

• Compiler-Directed Design Space Exploration for Caching and Prefetching Data in High-level Synthesis, N. Baradaran and P. Diniz (Univ. of Southern California)

• Post-Silicon Debug Using Programmable Logic Cores, B. R. Quinton and S. J. E. Wilton (Univ. of British Columbia)

• FPGA Organization for the Fast Path-Based Neural Branch Predictor, O. Cadenas, G. Megson and D. Jones (The Univ. of Reading)

• FPGA Implementation of an Excitatory and Inhibitory Connectionist Model for Motion Perception, C. Torres-Huitzil and B. Girau (LORIA-INRIA Lorraine)

• Spatiotemporal Simulation of a Single Living Cell, Y. Yamaguchi, T. Maruyama, R. Azuma and A. Konagaya (Univ. of Tsukuba)