ICFPT 05 » Tutorials

IEEE 2005 Conference on
Field-Programmable Technology (FPT)
http://www.icfpt.org/

Venue: Kent Ridge Guild House,
National University of Singapore
Singapore
December 11-14, 2005

Co-sponsorship by

IEEE Circuit and Systems Society
IEEE Singapore Section

School of Computing, National University of Singapore

Technical Co-sponsorship by

Electron Devices Society, IEEE

Tutorials

Sunday, December 11, 2005

To encourage participation, registration for the two high-quality tutorials will be free to all registered delegates of the conference.

Free transportation will be provided to ferry all conference delegates to the conference venue from the conference hotel.

Morning Tutorial

9am to 12.30pm

System Architectures and Design Patterns for Reconfigurable Computing

Speaker: Andre DeHon, Caltech

As numerous researchers in this community have demonstrated, there are many advantages to reconfigurable computing solutions. However, efficient reconfigurable solutions tend to be very different from the efficient sequential solutions with which most programmers are familiar. Reconfigurable computing allows and requires solutions which exploit parallelism at several levels of granularity. Nor do traditional ASIC design approaches adequately serve reconfigurable solutions; the low-level, fixed-capacity, cycle-by-cycle capture of traditional ASIC design does not expose or exploit the area-time tradeoffs which allow reconfigurable solutions to adapt to varying hardware capacity and performance requirements. As a result, today's conventional tools which derive from ASIC design and sequential processor programming tend to hinder rather than assist in developing efficient, scalable, reusable reconfigurable solutions.

Nonetheless, we can tame the reconfigurable design process, make it more systematic, make it more fully exploit the unique opportunities in reconfigurable solutions, and make designs more scalable by recognizing and exploiting a set of common and recurring organizational strategies and implementation techniques.

Almost all designs can be viewed as having one of a few gross, organizational "System Architectures" that identifies the high-level parallelism and communication structure in the design (e.g. Data Parallel, Streaming, Systolic, Cellular, Time-Multiplexed/VLIW). The more specialized of these "Architectures" provide structure and discipline to design organization allowing us to tame the challenges and costs of unconstrained parallel programming (e.g. non-determinism) and providing common solutions to design scaling. Identifying the space of "System Architectures" allows us to systematically consider organizational alternatives. Within a "System Architecture", we gain general lessons and solutions derived from a host of previous designs. Eventually, each
"System Architecture" can be the basis for specialized design tool support to further ease application analysis, optimization, and deployment.

Once we understand the gross parallelism and structure in our design, there remain a host of common tradeoffs, challenges, and optimizations which occur in reconfigurable designs. Since the opportunities and challenges are often different from those familiar to sequential processor designs (e.g. bit-level serialization and tuning, datapath specialization, spatial pipelining and retiming), new designers will often be particularly unfamiliar with these techniques. Consequently, it is useful to develop, teach, and share a set of "Design Patterns" for Reconfigurable Computing. These "Design Patterns" represent techniques and strategy elements---pieces of a design---that solve particular problems or exploit particular opportunities that may occur within a design. Together, these "System Architectures" and "Design Patterns" begin to give us a disciplined way to approach the systematic design of reconfigurable computing systems and design support for reconfigurable systems. They provide tools for complexity management and provide a way to share common and reusable lessons across various reconfigurable designs.

In this seminar we will introduce you to our emerging view of "System Architecture" and "Design Pattern" concepts for reconfigurable computing and discuss a number of examples of each. At this point, we are far from having a complete and definitive catalog of Architectures and Patterns or even being able to fully define their use. Nonetheless, we believe the core ideas are already valuable to improving and guiding design. Further, the key to maturing these ideas is engaging and involving the larger community in their development.
 

About the Speaker

Andre' DeHon received S.B., S.M., and Ph.D. degrees in Electrical Engineering and Computer Science from the Massachusetts Institute of Technology in 1990, 1993, and 1996 respectively. From 1996 to 1999, Andre' co-ran the BRASS group in the Computer Science department at the University of California at Berkeley. Since 1999, he has been an Assistant Professor of Computer Science at the California Institute of Technology. He is broadly interested in how we physically implement computations from substrates, including VLSI and molecular electronics, up through architecture, CAD, and programming models. He places special emphasis on spatial programmable architectures (e.g. FPGAs) and interconnect design and optimization.
 

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Afternoon Tutorial

2pm to 5.30pm

Reconfigurable Hardware Operating Systems

Speaker: Marco Platzner, University of Paderborn

SRAM-based FPGAs were introduced as high-end devices for implementing random logic in the mid-1980s. In the following years, FPGAs have found  a number of additional and novel uses in the design of embedded systems. One example is rapid prototyping and emulation. More recently, reconfigurable hardware is being used as an ASIC replacement with much shorter time-to-market and the novel ability to update hardware after product deployment. Today, the increasing densities of reconfigurable devices and the ongoing trend to integrate them with processors, memories, and special function blocks on configurable systems on a chip (CSoC) advocate more dynamic uses of the reconfigurable resources. A higher degree of dynamics is further facilitated by partial reconfiguration, a technique that allows us to reconfigure only a fraction of the resources while the remaining resources continue to execute.

Many promising application domains for reconfigurable computing systems combine high performance demands with frequent changes of their workloads. Examples for such application domains are wearable computing, mobile systems, and network processors. The dynamics in these systems is caused by user requests and packet flows in the communication networks. Mobile and wearable systems additionally operate in changing physical environments and contexts, which reflects in different types of workloads. Consequently, neither the set of functions nor the time at which these functions will be executed is exactly known in advance. A classic system design process with complete design-time synthesis and optimization is no longer possible. The required degree of flexibility paired with high computation demands asks for partially reconfigurable hardware that is operated in a true multitasking manner.

Multitasking reconfigurable hardware raises a number of novel issues, ranging from programming models to runtime systems. A programming model defines the executable objects and their interaction and provides the developer with a set of well-defined system services. A runtime system efficiently operates the hardware and software resources and resolves conflicts between executable objects. A programming model, together with a runtime system, forms a reconfigurable hardware operating system. The goal of this tutorial is to introduce to the emerging field of reconfigurable hardware operating systems, and to provide a survey over the main approaches taken and challenges faced. First, we will motivate operating system support for reconfigurable hardware and discuss the main components and services that may constitute an operating system layer. Then we will focus on the central problems of task and resource management, including task placement and scheduling, communication and I/O, as well as reconfiguration techniques. After reviewing several prototype systems, we will finally try to identify lines of further research.


About the speaker

Marco Platzner received the Dipl.-Ing. and the Ph.D. degrees in telematics from Graz University of Technology, Austria, in 1991 and 1996, respectively. From 1996 to 1998, he held a post-doctoral researcher position at GMD - German National Research Center for Information Technology. From 1997 to 1998, he was a Visiting Scholar at the Computer Systems Laboratory, Stanford University, USA. From 1998 to 2004, Marco Platzner was with the Computer Engineering and Networks Laboratory at the Swiss Federal Institute of Technology (ETH) Zurich, where he leads several projects in the area of reconfigurable computing systems. In 2004, he joined the University of Paderborn, Germany, as a full professor for Computer Engineering. His research interests cover reconfigurable computing, hardware-software codesign, and embedded systems.