I received my B.Comp. in Computer Engineering from National University of Singapore in June 2005. Since then, I continue to pursue a PhD degree here, under the supervision of A/P Abhik Roychoudhury and Prof Samarjit Chakraborty. I am also a member of the e-SAVVY (stands for embedded Software Analysis to Validate and VerifY) research group.

• System-level design of real-time and embedded systems
• Modeling and performance analysis/verification of embedded applications
• Architecture-aware timing analysis techniques

• Lei Ju, Bach Khoa Huynh, Samarjit Chakraborty, and Abhik Roychoudhury
  Context-Sensitive Timing Analysis of Esterel Programs
  ACM Design Automation Conference (DAC), 2009
  
  
• Lei Ju, Yun Liang, Samarjit Chakraborty, Tulika Mitra, and Abhik Roychoudhury
  Cache-aware Optimization of BAN Applications
  Springer Journal of Design Automation for Embedded Systems. (Invited paper for special issue on best papers from CODES+ISSS 2008)
  
  
• Lei Ju, Bach Khoa Huynh, Abhik Roychoudhury, and Samarjit Chakraborty
  A Systematic Classification and Detection of Infeasible Paths for Accurate WCET Analysis of Esterel Programs
  accepted to the Singaporean-French IPAL Symposium (SinFra), Singapore, February 2009
  
  
• Lei Ju, Bach Khoa Huynh, Abhik Roychoudhury, and Samarjit Chakraborty
  Performance Debugging of Esterel Specifications
  ACM Intl. Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Atlanta, USA, October 2008
  
  
• Yun Liang, Lei Ju, Samarjit Chakraborty, Tulika Mitra, and Abhik Roychoudhury
  Cache-aware Optimization of BAN Applications
  ACM Intl. Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Atlanta, USA, October 2008
  (nominated for best paper award)
  
  
• Lei Ju, Abhik Roychoudhury, and Samarjit Chakraborty
  Schedulability Analysis of MSC-based System Models
  14th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), St. Louis, MO, USA, April 2008
  
  
• Lei Ju, Samarjit Chakraborty, and Abhik Roychoudhury
  Accounting for Cache-related Preemption Delay in Dynamic Priority Schedulability Analysis
  IEEE Design Automation and Test in Europe (DATE), Nice, France, April 2007

• Internship @ IBM Research, Tokyo (Summer, 2009)
• Research Assistant (Since April 2007)
• Teaching Assistant for CS4272 Hardware-software Codesign (Semester 1 AY06/07, Semester 1 AY07/08)

• Research Achievement Award (2008/2009, School of Computing, National University of Singapore)