Sudipta Chattopadhyay
School of Computing,
National University of Singapore.
email : sudiptac at figure out the domain name
About Me
Hi, welcome to my homepage. I am Sudipta, currently a graduate student in the School of Computing at the National University of Singapore. My supervisor is A/P Abhik Roychoudhury and I am here a member of e-savvy research group. Previously I obtained my B.E. in Computer Science and Engineering from Jadavpur University, Calcutta (2005) and an M.E. in Internet Science and Engineering from Indian Institute of Science, Bangalore (2007). After my M.E., I spent almost 1.5 years in an EDA company Synopsys as an R&D engineer and joined NUS for my further studies in January, 2009.
Research Interests
Broadly in the area
of compilers,
program analysis, analysis of embedded softwares running on
multi-cores. Currently, I am working on software
timing analysis in
the presence of multi-core architectures, with a special focus on shared
resource usage (e.g. shared cache, shared bus). I am also interested in
various kind of memory optimizations for time predictable embedded
systems. With that in mind, I also work on compiler optimization
techniques for scratchpad memories, especially when the scratchpad
memory is shared among multiple processing elements. As a long term, I
also have some plan to analyze more complicated logics required for
multi-processing (e.g. coherence protocol).
Publications
Conferences and workshop
[RTSS] Unified Cache Modeling for WCET Analysis and Layout
Optimizations (abstract) (pdf)
Sudipta Chattopadhyay and Abhik Roychoudhury
30th IEEE Real-time System
Symposium (RTSS) 2009.
[SCOPES] Modeling shared Cache and Bus in Multi-core Platforms for Timing Analysis
(abstract) (pdf)
Sudipta Chattopadhyay, Abhik Roychoudhury
and Tulika Mitra
13th International Workshop on
Software and Compilers for Embedded Systems (SCOPES) 2010.
[LCTES] Static Bus Schedule aware Scratchpad Allocation in Multiprocessors (abstract) (pdf)
Sudipta Chattopadhyay and Abhik Roychoudhury
ACM SIGPLAN/SIGBED Conference on Languages, Compilers, Tools and Theory for Embedded Systems (LCTES) 2011.
[ECRTS] Bus-aware Multicore WCET Analysis through TDMA Offset Bounds (abstract) (pdf)
Timon Kelter, Heiko Falk, Peter Marwedel, Sudipta Chattopadhyay and Abhik Roychoudhury
23rd Euromicro Conference on Real-time Systems (ECRTS) 2011.
[RTSS] Scalable and Precise
Refinement of Cache Timing Analysis via Model Checking (abstract) (pdf)
Sudipta Chattopadhyay and Abhik Roychoudhury
32nd IEEE Real-time System
Symposium (RTSS) 2011.
Best paper award nomination
[RTSS] Timing Analysis of a Protected Operating System Kernel (abstract) (pdf)
Bernard Blackham, Yao Shi, Sudipta Chattopadhyay, Abhik Roychoudhury and Gernot Heiser
32nd IEEE Real-time System Symposium (RTSS) 2011.
[RTAS] A Unified WCET Analysis
Framework for Multi-core Platforms
(abstract) (pdf)
Sudipta Chattopadhyay, Chong Lee Kee, Abhik Roychoudhury, Timon Kelter, Peter
Marwedel and Heiko Falk
18th IEEE Real-time and Embedded Technology and Applications Symposium (RTAS)
2012.
Project website (contains the details of the tool, technical report with all the proofs and detailed experimental results)
Talks
[SCOPES] Modeling shared Cache and Bus in Multi-core Platforms for Timing Analysis (ppt)
13th International Workshop on Software and Compilers for Embedded Systems (SCOPES) 2010
[LCTES] Static Bus Schedule aware Scratchpad Allocation in Multiprocessors (ppt)
ACM SIGPLAN/SIGBED Conference on Languages, Compilers, Tools and Theory for Embedded Systems (LCTES) 2011.
[RTSS] Scalable and Precise
Refinement of Cache Timing Analysis via Model Checking
(ppt)
32nd IEEE Real-time System
Symposium (RTSS) 2011.
[RTAS]
A Unified WCET Analysis
Framework for Multi-core Platforms
(ppt)
18th IEEE Real-time and Embedded Technology and Applications Symposium (RTAS)
2012.
Personal
Links
Abstract
interpretation course by Cousot Our e-savvy research group