I am an Assistant Professor at the National University of Singapore working to develop high-efficiency microarchitectures that can meet the performance and needs of future IoT and server applications. The end of Dennard Scaling makes core power (and therefore overall processor efficiency) one key to improving performance. Our research group also has extensive experience in fast and accurate simulation methodologies and analytical modeling. These technologies form the foundation for our architecture research. Additionally, I co-develop the Sniper Multi-Core Simulator.

We are actively looking for PhD students interested in computer architecture research.

Contact us at tcarlson<AT>comp.nus.edu.sg; You can find me at COM2-03-43.

[Google Scholar][ORCID][DBLP]

Selected Publications

  1. Static Instruction Scheduling for High Performance on Limited Hardware
    K. A. Tran, T. E. Carlson, K. Koukos, M. Själander, V. Spiliopoulos, S. Kaxiras, and A. Jimborean
    IEEE Transactions on Computers (TC), 2017.

  2. A Graphics Tracing Framework for Exploring CPU+GPU Memory Systems
    A. Sembrant, T. E. Carlson, E. Hagersten, and D. Black-Schaffer
    IEEE International Symposium on Workload Characterization (IISWC), 2017.

  3. Non-Speculative Load-Load Reordering in TSO
    A. Ros, T. E. Carlson, M. Alipour, and S. Kaxiras
    International Symposium on Computer Architecture (ISCA), 2017.

  4. Exploring the Performance Limits of Out-of-order Commit
    M. Alipour, T. E. Carlson, and S. Kaxiras
    Computing Frontiers Conference (CF), 2017.

  5. Clairvoyance: Look-ahead Compile-time Scheduling
    K.-A. Tran, T. E. Carlson, K. Koukos, M. Själander, V. Spiliopoulos, S. Kaxiras, and A. Jimborean
    International Symposium on Code Generation and Optimization (CGO), 2017.

  6. Analytical Processor Performance and Power Modeling Using Micro-Architecture Independent Characteristics
    S. Van den Steen, S. Eyerman, S. D. Pestel, M. Mechri, T. E. Carlson, D. Black-Schaffer, E. Hagersten, and L. Eeckhout
    IEEE Transactions on Computers (TC), 2016.

  7. CoolSim: Statistical Techniques to Replace Cache Warming With Efficient, Virtualized Profiling Best Paper
    N. Nikoleris, A. Sandberg, E. Hagersten, and T. E. Carlson
    Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), 2016.

  8. Long Term Parking (LTP): Criticality-aware Resource Allocation in OOO Processors
    A. Sembrant, T. E. Carlson, E. Hagersten, D. Black-Shaffer, A. Perais, A. Seznec, and P. Michaud
    International Symposium on Microarchitecture (MICRO), 2015.

  9. Full Speed Ahead: Detailed Architectural Simulation at Near-Native Speed
    A. Sandberg, N. Nikoleris, T. E. Carlson, E. Hagersten, S. Kaxiras, and D. Black-Schaffer
    IEEE International Symposium on Workload Characterization (IISWC), 2015.

  10. The Load Slice Core Microarchitecture
    T. E. Carlson, W. Heirman, O. Allam, S. Kaxiras, and L. Eeckhout
    International Symposium on Computer Architecture (ISCA), 2015.

  11. Chrysso: An Integrated Power Manager for Constrained Many-core Processors
    S. S. Jha, W. Heirman, A. Falcón, T. E. Carlson, K. Van Craeynest, J. Tubella, A. González, and L. Eeckhout
    International Conference on Computing Frontiers (CF), 2015.

  12. Micro-architecture Independent Analytical Processor Performance and Power Modeling Nominated Best Paper
    S. Van den Steen, S. D. Pestel, M. Mechri, S. Eyerman, T. E. Carlson, D. Black-Schaffer, E. Hagersten, and L. Eeckhout
    International Symposium on Performance Analysis of Systems and Software (ISPASS), 2015.

  13. An Evaluation of High-Level Mechanistic Core Models
    T. E. Carlson, W. Heirman, S. Eyerman, I. Hur, and L. Eeckhout
    ACM Transactions on Architecture and Code Optimization (TACO), 2014.

  14. BarrierPoint: Sampled Simulation of Multi-threaded Applications Nominated Best Paper
    T. E. Carlson, W. Heirman, K. V. Craeynest, and L. Eeckhout
    International Symposium on Performance Analysis of Systems and Software (ISPASS), 2014.

  15. Undersubscribed Threading on Clustered Cache Architectures
    W. Heirman, T. E. Carlson, K. Van Craeynest, I. Hur, A. Jaleel, and L. Eeckhout
    International Symposium on High Performance Computer Architecture (HPCA), 2014.

  16. PCantorSim: Accelerating Parallel Architecture Simulation Through Fractal-based Sampling
    C. Jiang, Z. Yu, H. Jin, C. Xu, L. Eeckhout, W. Heirman, T. E. Carlson, and X. Liao
    ACM Transactions on Architecture and Code Optimization (TACO), 2013.

  17. Sampled Simulation of Multi-Threaded Applications Best Paper
    T. E. Carlson, W. Heirman, and L. Eeckhout
    International Symposium on Performance Analysis of Systems and Software (ISPASS), 2013.

  18. Power-Aware Multi-Core Simulation for Early Design Stage Hardware/Software Co-Optimization
    W. Heirman, S. Sarkar, T. E. Carlson, I. Hur, and L. Eeckhout
    Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT), 2012.

  19. Using Cycle Stacks to Understand Scaling Bottlenecks in Multi-threaded Workloads
    W. Heirman, T. E. Carlson, S. Che, K. Skadron, and L. Eeckhout
    IEEE International Symposium on Workload Characterization (IISWC), 2011.

  20. Sniper: Exploring the Level of Abstraction for Scalable and Accurate Parallel Multi-Core Simulations
    T. E. Carlson, W. Heirman, and L. Eeckhout
    International Conference for High Performance Computing, Networking, Storage and Analysis (SC), 2011.

  21. Using Fast and Accurate Simulation to Explore Hardware/Software Trade-offs in the Multi-Core Era
    W. Heirman, T. E. Carlson, S. Sarkar, P. Ghysels, W. Vanroose, and L. Eeckhout
    International Conference on Parallel Computing (ParCo), 2011.

  22. 3D Stacking of DRAM on Logic
    T. E. Carlson and M. Facchini
    Three Dimensional System Integration: IC Stacking Process and Design, 2011.

  23. Automated Pathfinding Tool Chain for 3d-stacked Integrated Circuits: Practical Case Study
    D. Milojevic, T. E. Carlson, K. Croes, R. Radojcic, D. F. Ragett, D. Seynhaeve, F. Angiolini, G. V. der Plas, and P. Marchal
    International Conference on 3D System Integration (3DIC), 2009.

  24. System-level Power/Performance Evaluation of 3D Stacked DRAMs for Mobile Applications
    M. Facchini, T. E. Carlson, A. Vignon, M. Palkovic, F. Catthoor, W. Dehaene, L. Benini, and P. Marchal
    Conference on Design, Automation and Test in Europe (DATE), 2009.

  25. Generic Multiphase Software Pipelined Partial FFT on Instruction Level Parallel Architectures
    M. Li, D. Novo, B. Bougard, T. E. Carlson, L. V. D. Perre, and F. Catthoor
    IEEE Transactions on Signal Processing, 2009.