I am an assistant professor at the National University of Singapore working to develop high-efficiency microarchitectures that can meet the performance and needs of future IoT and server applications. To do this, we explore a number of computer-architecture related areas, from energy-efficient processors, to secure chips and neuromorphic accelerators. The foundation for our architecture research comes from our experience in fast and accurate simulation methodologies and analytical modeling. Additionally, I co-develop the Sniper Multi-Core Simulator.

If you are interested in conducting research into energy-efficient processors, secure computing platforms, AI accelerators, programmable hardware, or simulation methodologies, contact us or see our open positions page for details.

[Google Scholar][ORCID][DBLP]; Contact us at tcarlson<AT>comp.nus.edu.sg; You can find me at COM3-02-10.

Navigate to Researchers, Alumni Researchers, Code and Projects, Works-in-Progress, Publications

Researchers in our Lab

PhD Students
บุรินทร์ อมรไพศาลนนท์ Burin Amornpaisannon (with Li Shiuan Peh) Artificial Intelligence Security
陈韵 Yun Chen Efficient Hardware Security
付逸豪 Yihao Fu Security
علی حاجی آبادی Ali Hajiabadi Efficient Hardware Security
刘常喜 Changxi Liu Simulation
آرش پاش رشید Arash Pashrashid Security
裴凌枫 Lingfeng Pei Efficient Hardware Security
അലൻ കണ്ടത്തുംതൊടുകയിൽ സാബു Alen Kandathumthodukayil Sabu Simulation
యశ్వంత్ తవ్వా Yaswanth Tavva (with Li Shiuan Peh) Security
项婷婷 Tingting Xiang Artificial Intelligence
于淼 Miao Yu Artificial Intelligence
Researchers
උදාරී චතුරංගී හිරන්තිකා කනේවල Udaree Kanewala Efficient Hardware
साई धवल फाये Sai Dhawal Phaye Security
Visiting Researchers
Teodor-Ştefan Duțu Teodor-Stefan Dutu Efficient Hardware
مونا هاشمی Mona Hashemi Security
Undergraduate Researchers
刘玮修 Wei Siew Liew Efficient Hardware
陈界铭 Kai Min (Russell) Tan Efficient Hardware

Alumni Researchers

Postdocs
Ανδρέας Διαβαστός Andreas Diavastos Efficient Hardware Security
వెంకట పవన్ కుమార్ మిరియాల Venkata Pavan Kumar Miriyala Artificial Intelligence
खुशबू रानी Khushboo Rani Security
PhD Students
न्यूटन Newton (with Virendra Singh) Efficient Hardware
이진호 Jinho Lee Efficient Hardware
Researchers
अर्चित अग्रवाल Archit Agarwal Security
आकांक्षा चौधरी Akanksha Chaudhari Simulation
നീതു ബാൽ മല്ല്യ Neethu Bal Mallya
Visiting Researchers
Ionuț Mihalache Ionut Mihalache Efficient Hardware
Undergraduate Researchers
陈彤 Tong Chen Artificial Intelligence
朱振忠 Kyle Timothy Ng Chu Artificial Intelligence Efficient Hardware
范达熠 Dayi Fan
冯彦恺 Yan Kai (Brandon) Foong Security
黄伟聪 Weicong Huang
康清玄 Ray Kang Artificial Intelligence
林俊宇 Chun Yu Lam Efficient Hardware
刘志洋 Zhiyang (Frank) Liu Efficient Hardware
卢育全 Keven Loo Efficient Hardware
刘骏 Jun (Keith) Low Efficient Hardware
黄文丰 Boon Hong Ng
Nguyễn Đăng Phúc Nhật Dang Phuc Nhat Nguyen
Srivatsa P
馮嘉俊 Vernon Pang
張偉政 Wei Zheng Teo
王继寒 Jihan Wang Artificial Intelligence
王宇辰 Yuchen Wang Simulation
俞悦 Yue Yu

Code Repositories and Project Sites

  1. Prime+Reset: Introducing A Novel Cross-World Covert-Channel Through Comprehensive Security Analysis on ARM TrustZone
  2. PrefetchX: Cross-Core Cache-Agnostic Prefetcher-Based Side-Channel Attacks
  3. GadgetSpinner: A New Transient Execution Primitive using the Loop Stream Detector
  4. Photon: A Fine-grained Sampled Simulation Methodology for GPU Workloads
  5. Capstone: A Capability-based Foundation for Trustless Secure Memory Access
  6. AfterImage: Leaking Control Flow Data and Tracking Load Operations via the Hardware Prefetcher
  7. Fast, Robust and Accurate Detection of Cache-based Spectre Attack Phases
  8. Elasticlave: An Efficient Memory Model for Enclaves
  9. LoopPoint: Checkpoint-driven Sampled Simulation for Multi-threaded Applications
  10. ELFies: Executable Region Checkpoints for Performance Analysis and Simulation
  11. Laser Attack Benchmark Suite
  12. QAOAToolkit: Bringing Quantum Optimization to the End User
  13. Directed Statistical Warming Through Time Traveling
  14. Behind the Scenes: Memory Analysis of Graphical Workloads on Tile-based GPUs
  15. An Evaluation of High-Level Mechanistic Core Models
  16. BarrierPoint: Sampled Simulation of Multi-threaded Applications
  17. Sniper: Exploring the Level of Abstraction for Scalable and Accurate Parallel Multi-Core Simulations

Works-in-progress

  1. Pac-Sim: Simulation of Multi-threaded Workloads Using Intelligent, Live Sampling
    C. Liu*, A. Sabu*, A. Chaudhari, Q. Kang, and T. E. Carlson
    arXiv preprint arXiv:2310.17089, 2023.
    Sampling Simulation

  2. Mitigating Power Attacks Through Fine-Grained Instruction Reordering
    Y. Chen*, A. Hajiabadi*, R. Poussier, A. Diavastos, S. Bhasin, and T. E. Carlson
    arXiv preprint arXiv:2107.11336, 2021.
    Security

Selected Publications

  1. Conjuring: Leaking Control Flow via Speculative Fetch Attacks
    A. Hajiabadi and T. E. Carlson
    Design Automation Conference (DAC), 2024.
    Security

  2. Levioso: Efficient Compiler-Informed Secure Speculation
    A. Hajiabadi, A. Agarwal, A. Diavastos, and T. E. Carlson
    Design Automation Conference (DAC), 2024.
    Security

  3. Prime+Reset: Introducing A Novel Cross-World Covert-Channel Through Comprehensive Security Analysis on ARM TrustZone
    Y. Chen*, A. Pashrashid*, Y. Wu, and T. E. Carlson
    Design, Automation and Test in Europe Conference and Exhibition (DATE), 2024.
    Security

  4. PrefetchX: Cross-Core Cache-Agnostic Prefetcher-Based Side-Channel Attacks
    Y. Chen, A. Hajiabadi, L. Pei, and T. E. Carlson
    International Symposium on High-Performance Computer Architecture (HPCA), 2024.
    Security

  5. GadgetSpinner: A New Transient Execution Primitive using the Loop Stream Detector
    Y. Chen*, A. Hajiabadi*, and T. E. Carlson
    International Symposium on High-Performance Computer Architecture (HPCA), 2024.
    Security

  6. Secure Run-Time Hardware Trojan Detection Using Lightweight Analytical Models
    B. Amornpaisannon, A. Diavastos, L.-S. Peh, and T. E. Carlson
    Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2024.
    Analytical Modeling Security

  7. Viper: Utilizing Hierarchical Program Structure to Accelerate Multi-core Simulation
    A. Sabu*, C. Liu*, and T. E. Carlson
    IEEE Access, 2024.
    Sampling Simulation

  8. HidFix: Efficient Mitigation of Cache-based Spectre Attacks Through Hidden Rollbacks
    A. Pashrashid, A. Hajiabadi, and T. E. Carlson
    International Conference on Computer-Aided Design (ICCAD), 2023.
    Security

  9. Photon: A Fine-grained Sampled Simulation Methodology for GPU Workloads
    C. Liu, Y. Sun, and T. E. Carlson
    International Symposium on Microarchitecture (MICRO), 2023.
    Sampling Simulation

  10. Multiply-and-Fire: An Event-driven Sparse Neural Network Accelerator
    M. Yu*, T. Xiang*, V. P. K. Miriyala, and T. E. Carlson
    ACM Transactions on Architecture and Code Optimization (TACO), 2023.
    Artificial Intelligence

  11. 3DRA: Dynamic Data-Driven Reconfigurable Architecture
    J. Lee, B. Amornpaisannon, A. Diavastos, and T. E. Carlson
    IEEE Access, 2023.
    Efficient Hardware

  12. Capstone: A Capability-based Foundation for Trustless Secure Memory Access
    J. Z. Yu, C. Watt, A. Badole, T. E. Carlson, and P. Saxena
    USENIX Security Symposium, 2023.
    Security

  13. A TTFS-based Energy and Utilization Efficient Neuromorphic CNN Accelerator
    M. Yu, T. Xiang, S. P., K. T. N. Chu, B. Amornpaisannon, Y. Tavva, V. P. K. Miriyala, and T. E. Carlson
    Frontiers in Neuroscience, 2023.
    Artificial Intelligence

  14. AfterImage: Leaking Control Flow Data and Tracking Load Operations via the Hardware Prefetcher
    Y. Chen, L. Pei, and T. E. Carlson
    International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2023.
    Security

  15. Fast, Robust and Accurate Detection of Cache-based Spectre Attack Phases
    A. Pashrashid, A. Hajiabadi, and T. E. Carlson
    International Conference on Computer-Aided Design (ICCAD), 2022.
    Security

  16. A Cross-Prefetcher Schedule Optimization Methodology
    R. Niţu, L. Pei, and T. E. Carlson
    IEEE Access, 2022.
    Efficient Hardware

  17. Efficient Instruction Scheduling Using Real-time Load Delay Tracking
    A. Diavastos and T. E. Carlson
    ACM Transactions on Computer Systems (TOCS), 2022.
    Efficient Hardware

  18. Elasticlave: An Efficient Memory Model for Enclaves
    Z. Yu, S. Shinde, T. E. Carlson, and P. Saxena
    USENIX Security Symposium, 2022.
    Security

  19. LoopPoint: Checkpoint-driven Sampled Simulation for Multi-threaded Applications
    A. Sabu, H. Patil, W. Heirman, and T. E. Carlson
    International Symposium on High-Performance Computer Architecture (HPCA), 2022.
    Sampling Simulation

  20. GraphWave: A Highly-Parallel Compute-at-Memory Graph Processing Accelerator
    J. Lee*, B. Amornpaisannon*, T. Mitra, and T. E. Carlson
    Design, Automation and Test in Europe Conference and Exhibition (DATE), 2022.
    Efficient Hardware

  21. Sentry-NoC: A Statically Scheduled NoC for Secure SoCs
    A. Shalaby, Y. Tavva, T. E. Carlson, and L.-S. Peh
    International Symposium on Networks-on-Chip (NOCS), 2021.
    Security

  22. Rectified Linear Postsynaptic Potential Function for Backpropagation in Deep Spiking Neural Networks
    M. Zhang, J. Wang, J. Wu, A. Belatreche, B. Amornpaisannon, Z. Zhang, V. P. K. Miriyala, H. Qu, Y. Chua, T. E. Carlson, and H. Li
    IEEE Transactions on Neural Networks and Learning Systems (TNNLS), 2021.
    Artificial Intelligence

  23. Ultra-Fast CGRA Scheduling to Enable Run Time, Programmable CGRAs
    J. Lee and T. E. Carlson
    Design Automation Conference (DAC), 2021.
    Efficient Hardware

  24. Tatami: Dynamic CGRA Reconfiguration for Multi-Core General Purpose Processing
    J. Lee and T. E. Carlson
    Work-in-Progress at Design Automation Conference (DAC), 2021.
    Efficient Hardware

  25. NOREBA: A Compiler-Informed Non-speculative Out-of-Order Commit Processor
    A. Hajiabadi, A. Diavastos, and T. E. Carlson
    International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2021.
    Efficient Hardware

  26. ELFies: Executable Region Checkpoints for Performance Analysis and Simulation
    H. Patil, A. Isaev, W. Heirman, A. Sabu, A. Hajiabadi, and T. E. Carlson
    International Symposium on Code Generation and Optimization (CGO), 2021.
    Performance Analysis Simulation

  27. SOTERIA: In Search of Efficient Neural Networks for Private Inference
    A. Aggarwal, T. E. Carlson, R. Shokri, and S. Tople
    arXiv preprint arXiv:2007.12934, 2020.
    Artificial Intelligence

  28. A Framework for Developing Critical Literacies in Computer Architecture Education
    S. L. Hepner and T. E. Carlson
    International Conference on Teaching, Assessment, and Learning for Engineering (TALE), 2020.

  29. Laser Attack Benchmark Suite
    B. Amornpaisannon, A. Diavastos, L.-S. Peh, and T. E. Carlson
    International Conference on Computer-Aided Design (ICCAD), 2020.
    Security Simulation

  30. QAOAToolkit: Bringing Quantum Optimization to the End User
    T. Anandakkoomar, P. Rebentrost, and T. E. Carlson
    Poster at International Workshop on Quantum Compilation (IWQC), 2020.

  31. Secure Your SoC: Building System-on-Chip Designs for Security
    S. Bhasin, T. E. Carlson, A. Chattopadhyay, V. B. Y. Kumar, A. Mendelson, R. Poussier, and Y. Tavva
    International System-on-Chip Conference (SOCC), 2020.
    Security Simulation

  32. PIM-GraphSCC: PIM-Based Graph Processing Using Graph’s Community Structures
    Newton, V. Singh, and T. E. Carlson
    Computer Architecture Letters (CAL), 2020.
    Efficient Hardware

  33. Directed Statistical Warming Through Time Traveling Nominated Best Paper
    N. Nikoleris, L. Eeckhout, E. Hagersten, and T. E. Carlson
    International Symposium on Microarchitecture (MICRO), 2019.
    Sampling Simulation

  34. Sampled Simulation of Task-Based Programs
    T. Grass, T. E. Carlson, A. Rico, G. Ceballos, E. Ayguadé, M. Casas, and M. Moreto
    IEEE Transactions on Computers (TC), 2018.
    Analytical Modeling Sampling

  35. Active Learning to Develop Key Research Skills in Master’s Level Computer Science Coursework
    S. L. Hepner and T. E. Carlson
    International Conference on Teaching, Assessment, and Learning for Engineering (TALE), 2018.

  36. SWOOP: Software-Hardware Co-Design for Non-Speculative Execute-Ahead, In-Order Cores
    K.-A. Tran, A. Jimborean, T. E. Carlson, K. Koukos, M. Själander, and S. Kaxiras
    The ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), 2018.
    Compilers Efficient Hardware

  37. Non-Speculative Load Reordering in Total Store Ordering
    S. Kaxiras, T. E. Carlson, M. Alipour, and A. Ros
    IEEE Micro Top Picks from the Computer Architecture Conferences (TopPicks), 2018.
    Efficient Hardware

  38. Maximizing Limited Resources: A Limit-Based Study and Taxonomy of Out-of-Order Commit
    M. Alipour, T. E. Carlson, D. Black-Schaffer, and S. Kaxiras
    Journal of Signal Processing Systems, 2018.
    Performance Analysis Efficient Hardware

  39. Power-performance Tradeoffs in Data Center Servers: DVFS, CPU Pinning, Horizontal, and Vertical Scaling
    J. Krzywda, A. Ali-Eldin, T. E. Carlson, P.-O. Östberg, and E. Elmroth
    Future Generation Computer Systems, 2018.
    Performance Analysis

  40. Behind the Scenes: Memory Analysis of Graphical Workloads on Tile-based GPUs Nominated Best Paper
    G. Ceballos, A. Sembrant, T. E. Carlson, and D. Black-Schaffer
    International Symposium on Performance Analysis of Systems and Software (ISPASS), 2018.
    Performance Analysis

  41. Transcending Hardware Limits With Software Out-of-order Processing Best of CAL
    T. E. Carlson, K.-A. Tran, A. Jimborean, K. Koukos, M. Själander, and S. Kaxiras
    International Symposium on High Performance Computer Architecture (HPCA), 2018.
    Efficient Hardware

  42. Static Instruction Scheduling for High Performance on Limited Hardware
    K. A. Tran, T. E. Carlson, K. Koukos, M. Själander, V. Spiliopoulos, S. Kaxiras, and A. Jimborean
    IEEE Transactions on Computers (TC), 2017.
    Compilers

  43. A Graphics Tracing Framework for Exploring CPU+GPU Memory Systems
    A. Sembrant, T. E. Carlson, E. Hagersten, and D. Black-Schaffer
    IEEE International Symposium on Workload Characterization (IISWC), 2017.
    Performance Analysis

  44. Non-Speculative Load-Load Reordering in TSO
    A. Ros, T. E. Carlson, M. Alipour, and S. Kaxiras
    International Symposium on Computer Architecture (ISCA), 2017.
    Efficient Hardware

  45. Exploring the Performance Limits of Out-of-order Commit
    M. Alipour, T. E. Carlson, and S. Kaxiras
    Computing Frontiers Conference (CF), 2017.
    Performance Analysis Efficient Hardware

  46. Clairvoyance: Look-ahead Compile-time Scheduling
    K.-A. Tran, T. E. Carlson, K. Koukos, M. Själander, V. Spiliopoulos, S. Kaxiras, and A. Jimborean
    International Symposium on Code Generation and Optimization (CGO), 2017.
    Compilers

  47. Analytical Processor Performance and Power Modeling Using Micro-Architecture Independent Characteristics
    S. Van den Steen, S. Eyerman, S. D. Pestel, M. Mechri, T. E. Carlson, D. Black-Schaffer, E. Hagersten, and L. Eeckhout
    IEEE Transactions on Computers (TC), 2016.
    Analytical Modeling

  48. CoolSim: Statistical Techniques to Replace Cache Warming With Efficient, Virtualized Profiling Best Paper
    N. Nikoleris, A. Sandberg, E. Hagersten, and T. E. Carlson
    Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), 2016.
    Simulation

  49. Long Term Parking (LTP): Criticality-aware Resource Allocation in OOO Processors
    A. Sembrant, T. E. Carlson, E. Hagersten, D. Black-Shaffer, A. Perais, A. Seznec, and P. Michaud
    International Symposium on Microarchitecture (MICRO), 2015.
    Efficient Hardware

  50. Full Speed Ahead: Detailed Architectural Simulation at Near-Native Speed
    A. Sandberg, N. Nikoleris, T. E. Carlson, E. Hagersten, S. Kaxiras, and D. Black-Schaffer
    IEEE International Symposium on Workload Characterization (IISWC), 2015.
    Simulation

  51. The Load Slice Core Microarchitecture
    T. E. Carlson, W. Heirman, O. Allam, S. Kaxiras, and L. Eeckhout
    International Symposium on Computer Architecture (ISCA), 2015.
    Efficient Hardware

  52. Epoch Profiles: Microarchitecture Application Analysis and Optimization
    T. E. Carlson, S. Nilakantan, M. Hempstead, and W. Heirman
    Computer Architecture Letters (CAL), 2015.
    Performance Analysis

  53. Chrysso: An Integrated Power Manager for Constrained Many-core Processors
    S. S. Jha, W. Heirman, A. Falcón, T. E. Carlson, K. Van Craeynest, J. Tubella, A. González, and L. Eeckhout
    International Conference on Computing Frontiers (CF), 2015.
    Efficient Hardware

  54. Micro-architecture Independent Analytical Processor Performance and Power Modeling Nominated Best Paper
    S. Van den Steen, S. D. Pestel, M. Mechri, S. Eyerman, T. E. Carlson, D. Black-Schaffer, E. Hagersten, and L. Eeckhout
    International Symposium on Performance Analysis of Systems and Software (ISPASS), 2015.
    Analytical Modeling

  55. An Evaluation of High-Level Mechanistic Core Models
    T. E. Carlson, W. Heirman, S. Eyerman, I. Hur, and L. Eeckhout
    ACM Transactions on Architecture and Code Optimization (TACO), 2014.
    Performance Analysis Simulation

  56. BarrierPoint: Sampled Simulation of Multi-threaded Applications Nominated Best Paper
    T. E. Carlson, W. Heirman, K. V. Craeynest, and L. Eeckhout
    International Symposium on Performance Analysis of Systems and Software (ISPASS), 2014.
    Sampling

  57. Undersubscribed Threading on Clustered Cache Architectures
    W. Heirman, T. E. Carlson, K. Van Craeynest, I. Hur, A. Jaleel, and L. Eeckhout
    International Symposium on High Performance Computer Architecture (HPCA), 2014.
    Efficient Hardware

  58. PCantorSim: Accelerating Parallel Architecture Simulation Through Fractal-based Sampling
    C. Jiang, Z. Yu, H. Jin, C. Xu, L. Eeckhout, W. Heirman, T. E. Carlson, and X. Liao
    ACM Transactions on Architecture and Code Optimization (TACO), 2013.
    Sampling

  59. Sampled Simulation of Multi-Threaded Applications Best Paper
    T. E. Carlson, W. Heirman, and L. Eeckhout
    International Symposium on Performance Analysis of Systems and Software (ISPASS), 2013.
    Sampling

  60. Power-Aware Multi-Core Simulation for Early Design Stage Hardware/Software Co-Optimization
    W. Heirman, S. Sarkar, T. E. Carlson, I. Hur, and L. Eeckhout
    Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT), 2012.
    Simulation

  61. Using Cycle Stacks to Understand Scaling Bottlenecks in Multi-threaded Workloads
    W. Heirman, T. E. Carlson, S. Che, K. Skadron, and L. Eeckhout
    IEEE International Symposium on Workload Characterization (IISWC), 2011.
    Performance Analysis

  62. Sniper: Exploring the Level of Abstraction for Scalable and Accurate Parallel Multi-Core Simulations
    T. E. Carlson, W. Heirman, and L. Eeckhout
    International Conference for High Performance Computing, Networking, Storage and Analysis (SC), 2011.
    Simulation

  63. Using Fast and Accurate Simulation to Explore Hardware/Software Trade-offs in the Multi-Core Era
    W. Heirman, T. E. Carlson, S. Sarkar, P. Ghysels, W. Vanroose, and L. Eeckhout
    International Conference on Parallel Computing (ParCo), 2011.
    Performance Analysis

  64. 3D Stacking of DRAM on Logic
    T. E. Carlson and M. Facchini
    Three Dimensional System Integration: IC Stacking Process and Design, 2011.
    Efficient Hardware

  65. Automated Pathfinding Tool Chain for 3D-stacked Integrated Circuits: Practical Case Study
    D. Milojevic, T. E. Carlson, K. Croes, R. Radojcic, D. F. Ragett, D. Seynhaeve, F. Angiolini, G. V. der Plas, and P. Marchal
    International Conference on 3D System Integration (3DIC), 2009.
    Performance Analysis

  66. System-level Power/Performance Evaluation of 3D Stacked DRAMs for Mobile Applications
    M. Facchini, T. E. Carlson, A. Vignon, M. Palkovic, F. Catthoor, W. Dehaene, L. Benini, and P. Marchal
    Conference on Design, Automation and Test in Europe (DATE), 2009.
    Performance Analysis Efficient Hardware

  67. Generic Multiphase Software Pipelined Partial FFT on Instruction Level Parallel Architectures
    M. Li, D. Novo, B. Bougard, T. E. Carlson, L. V. D. Perre, and F. Catthoor
    IEEE Transactions on Signal Processing, 2009.
    Efficient Hardware

* indicates equal contribution.