Google Scholar, ORCID, DBLP

Efficient Processors for the IoT hierarchy

My main research direction aims to optimize the efficiency of processors for the hierarchy of IoT devices, from edge computation to the backend servers. To accomplish this goal, we have been working to improve efficiency of general purpose processors that make up a large portion of the requirements for today’s compute infrastructure using techniques like those in the Load Slice Core and Out-of-Order Commit processors.

Selected Publications

Optimization, Hardware and Compilers

  1. Ros, A., Carlson, T. E., Alipour, M., & Kaxiras, S. (2017). Non-Speculative Load-Load Reordering in TSO. In Proceedings of the 44th Annual International Symposium on Computer Architecture (pp. 187–200). New York, NY, USA: ACM. https://doi.org/10.1145/3079856.3080220
  2. Alipour, M., Carlson, T. E., & Kaxiras, S. (2017). Exploring the Performance Limits of Out-of-order Commit. In Proceedings of the Computing Frontiers Conference (pp. 211–220). New York, NY, USA: ACM. https://doi.org/10.1145/3075564.3075581
  3. Tran, K.-A., Carlson, T. E., Koukos, K., Själander, M., Spiliopoulos, V., Kaxiras, S., & Jimborean, A. (2017). Clairvoyance: Look-ahead Compile-time Scheduling. In Proceedings of the 2017 International Symposium on Code Generation and Optimization (pp. 171–184). Piscataway, NJ, USA: IEEE Press. Retrieved from http://dl.acm.org/citation.cfm?id=3049832.3049852
  4. Sembrant, A., Carlson, T. E., Hagersten, E., Black-Shaffer, D., Perais, A., Seznec, A., & Michaud, P. (2015). Long Term Parking (LTP): Criticality-aware Resource Allocation in OOO Processors. In Proceedings of the 48th International Symposium on Microarchitecture (pp. 334–346). New York, NY, USA: ACM. https://doi.org/10.1145/2830772.2830815
  5. Carlson, T. E., Heirman, W., Allam, O., Kaxiras, S., & Eeckhout, L. (2015). The Load Slice Core microarchitecture. In 2015 ACM/IEEE 42nd Annual International Symposium on Computer Architecture (ISCA) (pp. 272–284). https://doi.org/10.1145/2749469.2750407
  6. Jha, S. S., Heirman, W., Falcón, A., Carlson, T. E., Van Craeynest, K., Tubella, J., … Eeckhout, L. (2015). Chrysso: An Integrated Power Manager for Constrained Many-core Processors. In Proceedings of the 12th ACM International Conference on Computing Frontiers (pp. 19:1–19:8). New York, NY, USA: ACM. https://doi.org/10.1145/2742854.2742885

Simulation, Sampling and Modeling

  1. Van den Steen, S., Eyerman, S., Pestel, S. D., Mechri, M., Carlson, T. E., Black-Schaffer, D., … Eeckhout, L. (2016). Analytical Processor Performance and Power Modeling Using Micro-Architecture Independent Characteristics. IEEE Transactions on Computers, 65(12), 3537–3551. https://doi.org/10.1109/TC.2016.2547387
  2. Nikoleris, N., Sandberg, A., Hagersten, E., & Carlson, T. E. (2016). CoolSim: Statistical techniques to replace cache warming with efficient, virtualized profiling. In 2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS) (pp. 106–115). https://doi.org/10.1109/SAMOS.2016.7818337
  3. Van den Steen, S., Pestel, S. D., Mechri, M., Eyerman, S., Carlson, T. E., Black-Schaffer, D., … Eeckhout, L. (2015). Micro-architecture independent analytical processor performance and power modeling. In 2015 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) (pp. 32–41). https://doi.org/10.1109/ISPASS.2015.7095782
  4. Carlson, T. E., Heirman, W., Eyerman, S., Hur, I., & Eeckhout, L. (2014). An Evaluation of High-Level Mechanistic Core Models. ACM Transactions on Architecture and Code Optimization (TACO), 11(3), 28:1–28:25. https://doi.org/10.1145/2629677
  5. Carlson, T. E., Heirman, W., Craeynest, K. V., & Eeckhout, L. (2014). BarrierPoint: Sampled Simulation of Multi-threaded Applications. In Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) (pp. 2–12).
  6. Carlson, T. E., Heirman, W., & Eeckhout, L. (2013). Sampled Simulation of Multi-Threaded Applications. In International Symposium on Performance Analysis of Systems and Software (ISPASS) (pp. 2–12).
  7. Carlson, T. E., Heirman, W., & Eeckhout, L. (2011). Sniper: Exploring the Level of Abstraction for Scalable and Accurate Parallel Multi-Core Simulations. In Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis (SC) (pp. 52:1–52:12). Retrieved from http://dx.doi.org/10.1145/2063384.2063454