The objective of this project is to design a real-time, high-throughput, low-power base station for future 5G wireless baseband processing using Software Defined Radio (SDR) technology. In particular, the project will be focused on many-core architecture design for high-throughput processing, real-time operating systems (RTOS) design to fully leverage the underlying architecture, and an end-to-end performance evaluation with realistic 5G applications and their corresponding network traffic.
The main challenge in 5G wireless baseband processing is the 10x increase in throughput and 10 fold reductions in latency. The physical layer processing is the most computationally demanding component in the base station protocol stack. Traditionally, the physical layer has been implemented using customized fixed-function hardware accelerator and DSP (digital signal processing) cores. However, these designs are inflexible in the face of updates in the standard and supporting multiple standards as required by SDR.
Software-programmable processors can offer easy migration path. However, current many-core architectures (both commercial and academic) are far from achieving 5G throughput. The goal of this project is to design fully-programmable, power-efficient many-core architecture for real-time, high-throughput processing of the physical layer in a base station.