Performance Debugging of Embedded Systems

   
Presenters: Samarjit Chakraborty  & Abhik Roychoudhury
School of Computing

National University of Singapore

 

Date: 7 January, 2007  (Afternoon session) with VLSI 2007

The tutorial has taken place. We thank all those attended and showed interest by asking numerous interesting questions during & after the tutorial.

Outline:

 

Modern embedded systems are often associated with stringent performance, cost and power constraints. Hence, designing such systems involve guaranteeing that these constraints are met, apart from the usual functional validation. Such systems typically consist of a heterogeneous collection of processors, specialized memory subsystems, and partially programmable or fixed-function components. This heterogeneity, coupled with issues such as hardware/software partitioning, mapping, scheduling, etc., leads to a large number of design possibilities, thereby making performance debugging of such systems a difficult problem. This tutorial will provide a comprehensive overview of the recent developments on this front, with focus on timing analysis. In particular we will cover the following issues:

i)                     does a design meet its timing requirements,

ii)                   if not, then which parts of the system are responsible for the timing violation, and

iii)                  once they are identified, then how should the design be suitably modified?  

The topics covered will span over the major abstraction levels involved in embedded systems design, starting from software analysis and micro-architectural modeling, to modeling of resource sharing and communication at the system level. Apart from discussing the relevant modeling and analysis techniques, the tutorial will also cover practical case studies and tool demos. In particular, we plan to demo two tools: one covering software timing analysis, and the other focusing on system level performance analysis. We will conclude the tutorial with future directions in this research area with focus on integrated performance analysis/debugging at software and system level.

 

Targeted Audience:

The level of the tutorial will be from introductory to intermediate. The material to be presented would be useful to researchers, students, embedded software developers and engineers working on system-level design of real-time embedded systems. The emphasis will be on state-of-the-art techniques and tools for debugging and validating non-functional or performance constraints arising in complex embedded systems. No background in formal analysis techniques or VLSI design automation techniques will be assumed and the lectures will focus on a diverse set of modelling and analysis techniques, with detailed self-contained examples. We will start with concrete applications of performance debugging in embedded system design flows.

References:
  1. Tulika Mitra and Abhik Roychoudhury, Worst-case Execution Time and Energy Analysis, Chapter in the Compiler design Handbook (2nd Edition), Y.N. Srikant and Priti Shankar Editors, To appear.

  2. Xianfeng Li, Abhik Roychoudhury, Tulika Mitra: Modeling Out-of-Order Processors for WCET Analysis. Real-time Systems Journal, 34(3), 2006.

  3. Xianfeng Li, Tulika Mitra and Abhik Roychoudhury, Modeling Control Speculation for Timing Analysis Real-Time Systems Journal, Springer, 29(1), 2005.

  4. Lothar Thiele, Ernesto Wandeler, and Samarjit Chakraborty
    A Stream-Oriented Component Model for Performance Analysis of Multiprocessor DSPs
    IEEE Signal Processing Magazine, 22(3):38--46, special Issue on Hardware/Software Co-design for DSP, 2005

  5. Samarjit Chakraborty, Simon K┨nzli, Lothar Thiele, Andreas Herkersdorf, and Patricia Sagmeister
    Performance Evaluation of Network Processor Architectures: Combining Simulation with Analytical Estimation
    Computer Networks, 41(5):641--665, 2003

  6. Samarjit Chakraborty, Thi Xuan Linh Phan, and P.S. Thiagarajan
    Event Count Automata: A State-based Model for Stream Processing Systems
    IEEE Real-Time Systems Symposium (RTSS), Miami, Florida, December 2005