Overview

Theory of Operation

Block Diagram

[Block Diagram]

Details of Operation

The Basic Microinstruction Sequencer has a simple datapath structure as shown in the figure above. The multiplexor is used to chose between 3 possible outputs: direct input (D), the internal program counter register (PC) and the stack (F). Selection is determined by the output of the selector bits from an Instruction ROM. The set of eight instructions supported by the BSM is encoded in the PLA (please refer to the following section).

Depending on the inputs I2-I0 and the condition bits /CC and /CCEN, the ROM sends different signals to the other modules to achieve different effects. The table in the next section provides more information on the detailed operation. In general, there are 3 classes of instructions: branch instructions, stack operations and assertions. There is also a special RESET instruction to force the initial states of the chip to zero at the beginning of operation or if a reset is required.

The 12-bit output Y of the chip is piped through a tristate buffer and controlled by an input /OE. This allows the outputs to be connected directly to a system bus if desired. Instructions can be repeated by disabling CI and preventing the Program Counter from incrementing. Since the stack has limited capacity, the chip can only support up to 8 levels of subroutine branching. When the stack is full, /FULL is asserted. Further attempts to push data onto the stack will cause the stack to wrap around, overwriting the earliest piece of data; in the same manner, popping an empty stack will place non-meaningful data on the Y outputs but leave the stack pointer in an unspecified position. In general, users should not push more than eight pieces of data onto the stack or try to pop and empty stack; there are no guarantees on the behavior of the stack once the abstraction is violated.

The estimated clock load the the entire chip is 4pF. A clock buffer will be used to ensure that the clock signal will not degrade too much due to this capacitance. This clock buffer can drive the 4pF load with a propogation delay of 3ns and a rise time of 4.5ns.

Pinout

[Pinout for the chip]

Division of Responsibilities

Team Member	Responsibility
Ben Leong benleong@mit.edu	Design, testing and layout of the Instruction ROM. Design and layout of clock driver. Layout and testing of the stack pointer. Testing of the integrated system. Floorplan management. Documentation coordinator.
Mike Sy mike_sy@mit.edu	Design of the stack pointer unit that must handle push, pop, hold, and clear; design, layout and testing of the 8 word by 12-bit stack memory. Documentation of the stack pointer and the stack.
Steve Lee sclee@mit.edu	Design, testing and layout of the instruction multiplexer, microprogram counter/register, and program counter incrementer. Checking of timing specifications; Top-level routing. Documentation of the datapath, not including the stack.

Comments to benleong@mit.edu or mike_sy@mit.edu or sclee@mit.edu
Last updated 11/21/96.