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Publications on Chronos

• [RTSS'09] Unified Cache Modeling for WCET Analysis and Layout Optimizations
  Sudipta Chattopadhyay and Abhik Roychoudhury
  IEEE Real-time System Symposium (RTSS) 2009.
  


• Chronos: A Timing Analyzer for Embedded Software
  Xianfeng Li, Yun Liang, Tulika Mitra, Abhik Roychoudhury
  Science of Computer Programming, Special issue on Experimental Software and Toolkit, 69(1-3), December 2007
  


• [RTS'06] Modeling Out-of-Order Processors for WCET Analysis
  Xianfeng Li, Abhik Roychoudhury, Tulika Mitra
  To appear in Real-Time Systems Journal
  [A much expanded version of RTSS'04 paper on the same topic]
  
  
• Microarchitecture Modeling for Timing Analysis of Embedded Software
  Xianfeng Li
  PhD Thesis, School of Computing, National University of Singapore     
  

• [RTS'05] Modeling Control Speculation for Timing Analysis
  Xianfeng Li, Tulika Mitra and Abhik Roychoudhury
  Real-Time Systems Journal, 29(1), January 2005
  [An extended version of DAC'03 and ISSS'02 paper]
  

• [RTSS'04] Modeling Out-of-Order Processors for Software Timing Analysis  
  Xianfeng Li, Abhik Roychoudhury and Tulika Mitra
  25th IEEE Real-Time Systems Symposium (RTSS) 2004 [slides]
  

• [DAC'03] Accurate Timing Analysis by Modeling Caches, Speculation and their Interaction  
  Xianfeng Li, Tulika Mitra and Abhik Roychoudhury
  40th ACM/IEEE Design Automation Conference (DAC), June 2003 [slides]
  

• [ISSS'02] Timing Analysis of Embedded Software for Speculative Processors
  Tulika Mitra, Abhik Roychoudhury and Xianfeng Li
  ACM International Symposium on System Synthesis (ISSS), October 2002 [slides]
  

• [WCET'02] A Framework to Model Branch Prediction for WCET Analysis
  Tulika Mitra, Abhik Roychoudhury
  2nd Workshop on Worst Case Execution Time Analysis (WCET), June 2002
  

Related Publications

• [RTSS'09] Timing Analysis of Concurrent Programs running on Shared Cache Multi-cores
  Yan Li, Vivy Suhendra, Yun Liang, Tulika Mitra and Abhik Roychoudhury
  IEEE Real-time System Symposium (RTSS) 2009.
  


• [DAC'06] Efficient Detection and Exploitation of Infeasible Paths for Software Timing Analysis
  Vivy Suhendra,  Tulika Mitra,  Abhik Roychoudhury,  Ting Chen
  43rd ACM/IEEE Design Automation Conference, July 2006


• [RTAS'06] Estimating the Worst-Case Energy Consumption of Embedded Software
  Ramkumar Jayaseelan, Tulika Mitra, Xianfeng Li.
  12th IEEE Real-Time and Embedded Technology and Applications Symposium, April 2006 [slides]

• [RTSS'05] WCET Centric Data Allocation to Scratchpad Memory
  Vivy Suhendra,  Tulika Mitra,  Abhik Roychoudhury,  Ting Chen.
  26th IEEE Real-time Systems Symposium, December 2005
  
  
• [ICDCIT'05] Analyzing Loop Paths for Execution Time Estimation
  Abhik Roychoudhury, Tulika Mitra, Hemedra Singh Negi
  International Conference on Distributed Computing and Internet Technology, December 2005. LNCS vol. 3347
  
  
• [CODES+ISSS'05] Satisfying Real-Time Constraints with Custom Instructions
  Pan Yu, Tulika Mitra
  ACM International Conference on Hardware/Software Codesign and System Synthesis, September 2005 [slides]
  
  
• [WCET'05] Exploiting Branch Constraints without Exhaustive Path Enumeration
  Ting Chen, Tulika Mitra, Abhik Roychoudhury, Vivy Suhendra
  5th International Workshop on Worst-Case Execution Time Analysis, July 2005    
    
• [WCET'04] Simplifying WCET Analysis by Code Transformations
  Hemendra Singh Negi, Abhik Roychoudhury, Tulika Mitra
  4th International Workshop on Worst-Case Execution Time Analysis, June 2004
  
  
• [CODES+ISSS'03] Accurate Estimation of Cache-Related Preemption Delay
  Hemendra Singh Negi, Tulika Mitra, Abhik Roychoudhury
  ACM International Conference on Hardware/Software Codesign and System Synthesis, October 2003