Titlepage | Introduction
| Overview | ROM | Datapath
| Testing | Conclusion | References.
Layout
The layout for the chip was done hierarchically as several datapaths.
The chip uses mostly metal1 wiring for intracell connections.
Intercell horizonal connections are also made with metal1 wire, while
intercell vertical connections are made with metal2 wire. Well and
substrate contacts are placed once about every 50um. Vdd and ground
are routed around the chip in a ring so that all components can tap
vdd and ground from either the side or the top.
Floorplan
![[Floorplan]](floorplan.gif)
Toplevel layout
![[Toplevel Layout Schematic]](chip_layout.gif)
Layout for Instruction ROM
![[Instruction ROM Layout Schematic]](rom_layout.gif)
Layout for Stack Pointer
![[Stack Pointer Layout Schematic]](stackptr_layout.gif)
Layout for Stack
![[Stack Layout Schematic]](stack_layout.gif)
Layout for Datapath
![[Datapath Layout Schematic]](datapath_layout.gif)
Layout for Clock Driver
![[Clock Driver Layout Schematic]](clock_driver_layout.gif)
Comments to benleong@mit.edu
or mike_sy@mit.edu or sclee@mit.edu
Last updated 11/21/96.
Titlepage | Introduction
| Overview | ROM | Datapath
| Testing | Conclusion | References.