Embedded system design has become important in the recent years with the integration of computing components in devices of everyday use. Most of these applications must give guaranteed responses within a time bound and should consume low power. To satisfy the power and timing guarantees, embedded system designers often perform extensive simulation of the application code. This is to ensure that the time and power consumption lies within a specified budget under all circumstances. However, simulation might miss corner cases and extensive simulation is infeasible for designs with tight time-to-market constraint.

This project takes a two-pronged approach for developing high-assurance embedded systems with strict power and timing budget. First, we employ static analysis techniques to estimate the worst-case power and performance bound. This involves a combination of programming language level analysis with micro-architectural modeling of the platform. Our focus here is to study the effect of micro-architectural features with unpredictable dynamic behavior (e.g., caches, speculation, interconnection network) on timing and power consumption.

Secondly, we are developing software design patterns and hardware features to make the run-time behavior of embedded code more predictable. This will allow the designer to avoid complicated modeling of hardware features for timing/power estimation. The main challenge here is to develop sufficient conditions under which fragments of the application code can be certified as "predictable" (and hence amenable to efficient timing/power estimation). Furthermore, we are studying source level transformations under which code with unpredictable run-time behavior can be converted to semantically equivalent "predictable" code.

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