Real-time embedded systems are ubiquitous, appearing in diverse application domains such as avionics, automobiles, and consumer electronics. For safety-critical embedded systems, system design from high-level behavioral models (such as Simulink, Stateflow, or synchronous programming models like Esterel) is of paramount importance. In such design flows, the entire system description is developed as a high-level model and code is automatically generated from these models.

Clearly, for model-based design of real-time control software, we need to support timing analysis at the model level. However, conventional techniques for timing or schedulability analysis are not mature enough for this purpose. This is because (a) the task models usually considered for system-level schedulability analysis are not powerful enough to be used for models of computation like State Diagrams, and (b) many simplifying assumptions made in the models (such as the synchrony hypothesis in the synchronous programming languages) are currently not supported/validated by the lower-level timing analyzers. In this project, we will attempt to overcome these difficulties and develop a model-level timing analysis framework.

Research Directions

We will build on (and exploit) our past work on system- and software-level timing analyzers. In particular, we plan to leverage on our past efforts with the Chronos WCET analyzer for software timing analysis.

Our main strategy will be to exploit the recent advances in program-level timing analysis and micro-architecture modeling and integrate them with model-level timing analysis techniques. Modern day UML-based behavioral system modeling tools (e.g. those based on State Diagrams) support automated code generation. We will study how platform-aware time-safety checking can be performed for the generated code, and results from such timing analysis can be replayed back at the model level. In this project, we plan to pursue the following research directions.

• Relating software timing analysis to high-level behavioral models
• Relating system-level performance analysis to high-level behavioral models
• Validating idealized timing assumptions made at model level via platform-aware software analysis

An important technical contribution of this project will be to seamlessly integrate platform-aware software timing analysis into the compilation process of reactive languages like Esterel and Lustre.

People

Faculty Members

• Abhik Roychoudhury (Principal Investigator)
• Samarjit Chakraborty (Co-Principal Investigator)

PhD Students

• Lei Ju
• Bach Khoa Huynh

Publications

• Accounting for Cache-related Preemption Delay in Dynamic Priority Schedulability Analysis (pdf)  Lei Ju, Samarjit Chakraborty, Abhik Roychoudhury  Design Automation and Test in Europe (DATE) 2007.
• Schedulability Analysis of MSC-based System Models (pdf) Lei Ju, Abhik Roychoudhury, Samarjit Chakraborty
  14th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS) 2008.
• Scratchpad Allocation for Concurrent Embedded Software, Vivy Suhendra, Abhik Roychoudhury and Tulika Mitra, ACM Intl Conf on Hardware/Software Codesign and System Synthesis (CODES+ISSS) 2008.
• Performance Debugging of Esterel Specifications Lei Ju, B K Huynh, Abhik Roychoudhury and Samarjit Chakraborty, ACM Intl Conf on Hardware/Software Codesign and System Synthesis (CODES+ISSS) 2008.
• Debugging Statecharts via Model-code Traceability Liang Guo and Abhik Roychoudhury,  International Symposium on Leveraging Applications of Formal Methods, Verification and Validation (ISoLA) 2008, Invited.

• Context-Sensitive Timing Analysis of Esterel Programs Lei Ju, Bach Khoa Huynh, Samarjit Chakraborty and Abhik Roychoudhury, ACM Design Automation Conference (DAC) 2009.

• Footprinter: Roundtrip Engineering via Scenario and State based Models Ankit Goel, Bikram Sengupta and Abhik Roychoudhury,  ACM International Conference on Software Engineering (ICSE) 2009, Short paper.