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Results for Schematic-Level Testing of Integrated System

The following are the results for our testing of the integrated system at the schematic level. It can be noticed that the /FULL does not seem to be doing the right thing. This was one problem discovered while testing the integrated system at the schematic leve. It was fixed subsequently in the layout.

[Integrated Simulation Timing Diagram 1]

[Integrated Simulation Timing Diagram 2]

[Integrated Simulation Timing Diagram 3]

[Integrated Simulation Timing Diagram 4]

[Integrated Simulation Timing Diagram 5]

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Comments to benleong@mit.edu or mike_sy@mit.edu or sclee@mit.edu
Last updated 11/21/96.

Titlepage | Introduction | Overview | ROM | Datapath | Layout | Testing | References.