Schematic-Level Testing of Integrated System

Overview

After schematics of the individual modules were found to be working, they were integrated and the resulting unit was used as a subunit for a MicroController Unit (MCU). The circuit diagram for the MCU is shown below. A set of test microcode was written to test all the functions of the sequencer. This code was compiled into a ROM schematic, mcu.S, using a C program called makeROM, written by Jamie Cho.

Circuit Diagram for Test MCU

[MCU Test Results]

Assembly Code

Instruction Word Organization:
  conditional statements       iiiuc aaaaaaa
  assertion statement          111ss sssssss

c=1 TEST
c=0 FALSE

start:
0	CJMP TEST end-loop;			0100 1001 1101   49d
1	ASSERT 000000000;			1110 0000 0000   e00
2	ASSERT 000000001;			1110 0000 0001   e01
3	ASSERT 000000010;			1110 0000 0010   e02
4	JSRP  quick-jump-loop;			0011 0001 0100   314
5	ASSERT 000000100;			1110 0000 0100   e04
6       CJMP FALSE jump-loop;			0100 0001 0110	 416	
7	ASSERT 000001000;			1110 0000 1000   e08
8       CJSRP TEST jump-loop;			0010 1001 0110	 296
9	ASSERT 000010000;			1110 0001 0000   e10
10	CPUSH TEST;				0110 1000 0000   680
11	ASSERT 000100000;			1110 0010 0000   e20
12	CPOP TEST;			        1000 1000 0000   880
13	CPUSH TEST;				0110 1000 0000   680
14	ASSERT 001000000;			1110 0100 0000   e40
15	CRTN TEST;				1010 1000 0000   a80
16	PUSH;					0111 0000 0000   700
17	JMP test-cjp;				0101 0001 1001	 519	
back-to-main-loop: 10010			
18	ASSERT 010000000;			1110 1000 0000   e80
19	JMP reset;				0101 0001 1011   51b
quick-jump-loop: 10100			
20	ASSERT 100000000;			1111 0000 0000   f00
21	RTN;					1011 0000 0000	 b00
jump-loop: 10110
22	ASSERT 000000011;			1110 0000 0011   e03
23	CRTN TEST;				1010 1000 0000   a80
24	JMP jump-loop;				0101 0001 0110   516
test-cjp: 11001						
25	ASSERT 000001100;			1110 0000 1100   e0c
26	JPP back-to-main-loop;                  1101 0001 0010   d12
reset: 11011			
27	ASSERT 000110000;			1110 0011 0000   e30
28	LDZ;					0000 0000 0000   000
end-loop: 11101			
29	PUSH;					0111 0000 0000   700
30	PUSH;					0111 0000 0000   700
31	PUSH;					0111 0000 0000   700
32	PUSH;					0111 0000 0000   700
33	PUSH;					0111 0000 0000   700
34	PUSH;					0111 0000 0000	 700		
35	PUSH;					0111 0000 0000   700
36	PUSH;					0111 0000 0000   700
37	POP;					1001 0000 0000   900
38	POP;					1001 0000 0000   900
39	POP;					1001 0000 0000   900
40	POP;					1001 0000 0000   900
41	POP;					1001 0000 0000   900
42	POP;					1001 0000 0000   900
43	POP;					1001 0000 0000   900
44	POP;					1001 0000 0000   900
45	JMP end-loop;				0101 0001 1101   51d

Results

Initial simulations revealed a number of problems with the system, all of which were promptly fixed. Most of which were produced by race conditions arising from stack operations. The results for the schematic simulation are available.

System Timing

The system timing specifications are derived from the following simple programming executing on the schematic version of the sequencer.

XXXX JUMP ZERO
0001 CONTINUE
0002 JUMP SUBROUTINE 2048 
2048 CONTINUE
2049 RETURN FROM SUBROUTINE
0005 XXXXXXXXXXXXXXXXXXXXXX

Executing the above program using Lsim produced the following plot.

[System Timing]

The plot shows that the worst delay through the chip occurs when it is executing a sequential instruction at location 2047. In this situation, the incrementer carry is propagating through all the carries. This worst delay approximately 24ns. Taking into account that the actual delay of the pop in the program may actually be longer because the output of a pop is normally only available at the low part of the clock cycle, we expect to be able to run the chip at 30Mhz.

Note that this simulation does not account for the delay of the external program ROM and the delay of the inputs and outputs through the pads of the chip. The chip can be expected to run at approximately 20Mhz taking these factors into account.

Comments to benleong@mit.edu or mike_sy@mit.edu or sclee@mit.edu
Last updated 11/21/96.