Assembly

MIPS instructions will be translated to machine code for actual execution. This section will show you how to translate MIPS assembly code into binary patterns. Furthermore, we will try to explain some "strange facts" from previous section:

• Why is immediate limited to 16 bits?
• Why is shift amount only 5 bits?

Answering these questions will prepare us to "build" a simple MIPS processor in later lectures!

Basic Encoding

Each MIPS instruction has a fixed-length of 32 bits. So, all relevant information for an operation must be encoded within these bits! There are also some other additional challenge which is to make the instruction encodings as regular as possible. In other words, there should be small number of formats with as few variations as possible. This will also make our MIPS processor design easier later.

MIPS Instruction Classification

Instructions are classified according to their operands. Instructions with the same operand types have the same encoding.

R-Format

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op $rd, $rs, $rt
op $rd, $rs, shamt

R-format instructions use either:

• 2 source registers (i.e., $rs and $rt) and 1 destination register (i.e., $rd).
  • add, sub, and, or, nor, slt, etc¹.
• 1 source registers (i.e., $rs), 1 destination register (i.e., $rd), and one shift amount.
  • sll, srl, etc.

Although there may seem to be two variants, in the end we have enough number of bits to not use all of them and select either to use $rt or shamt.

I-Format

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op $rt, $rs, immediate
op $rt, immediate($rs)

I-format instructions use either:

• 1 source register (i.e., $rs), 1 destination register (i.e., $rt) and 1 immediate value.
  • addi, andi, ori, slti, lw, etc.
• 2 source registers (i.e., $rs and $rt) and 1 immediate value.
  • sw, beq, bne, etc.

Although there may seem to be two variants, it is simply a matter of whether we write into the register or not.

J-Format

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op immediate

J-format instructions use only one immediate value.