Instruction Set Architecture

We take a quick detour to see other instruction set architecture (ISA). Some of the topics here may be similar to the topic introduced when we talk about MIPS but may be generalised further to include other architecture.

To illustrate, we will first tell you about one of the most famous battles in the design philosophies for ISA. There are two camps here.

We will not be comparing those two. Instead, we will discuss the 5 design concepts in ISA design.

1. Data Storage
2. Memory Addressing Modes
3. Operations in the Instruction Set
4. Instruction Formats
5. Encoding the Instruction Set

Objective

Concept #1: Data Storage

Modern computers employe the von Neumann architecture for which data and program are stored in memory. However, in the case of processors, storage architecture concerns more with:

• Where do we store the operands so that the computation can be performed?
• Where do we store the computation result afterwards?
• How do we specify the operands?

Some of the major storage architecture includes:

1. Stack Architecture: Operands are implicitly on top of the stack.
   • Examples: Python bytecode assumes stack architecture.
2. Accumulator Architecture: One operand is implicitly in the accumulator (a special register).
   • Examples: IBM 701, DEC PDP-8.

3. General-Purpose Register Architecture (GPR): Only explicit operands. There are two major sub-architecture:

   1. Register-Memory Architecture: One operand in memory.
      • Examples: Motorola 68000, Intel 80386.

   2. Register-Register Architecture: All operands in register. Also called load-store architecture.

      • Examples: MIPS, DEC Alpha.

4. Memory-Memory Architecture: All operands in memory.

   • Examples: DEC VAX.

The most common storage design for modern processor is the general-purpose register (GPR). This includes many of the RISC processors (e.g., MIPS and ARM processors) which typically use register-register (i.e., load/store) architecture. On the other hand, CISC processors (e.g., IA32) use a mixture of register-register and register-memory architecture.

Concept #2: Memory Addressing Mode

We are concerned with memory locations and addresses, the addressing modes as well as the memory content.

Memory Address

Given k-bit address, the address space is of size 2^k. Each memory transfer consists of one word of n bits.

Memory Content: Endianness

Endianness is concerned with the relative ordering of the bytes in a multiple-byte word stored in memory. This is another major battle in the design philosophies.

The name comes from the root-word "end"¹. In particular, which end should be in front. In other words, whether the most significant byte (i.e., big-end) should be at the lowest address or should it be the least significant byte (i.e., little-end). Note that here we order the byte and not the bit. There are two major camps here:

	Big-Endian	Little-Endian
Order	Most significant byte stored in lowest address (big-end)	Least significant byte stored in lowest address (little-end)
Processor	IBM 360/370, Motorola 6800, MIPS, SPARC	Intel 80x86, DEC VAX, DEC Alpha
Example	0xDE AD BE EF is stored as	0xDE AD BE EF is stored as

Addressing Modes

Addressing mode is the ways to specify an operand in an assembly language. In MIPS, there are only 3 addressing modes:

1. Register: Operand is in a register (e.g., add $t1, $t2, $t3).
2. Immediate: Operand is specified in the instruction directly (e.g., addi $t1, $t2, 98).
3. Displacement: Operand is in memory with address calculated as Base + Offset (e.g., lw $t1, 20($t2)).

There are, however, other addressing modes summarised below:

Concept #3: Operations in Insturctions Set

There are some standard operations that are common to most modern processors:

Additionally, we can look at the frequently used instructions. The idea is that since these instructions are frequently used, it makes sense to make these instructions fast!

Concept #4: Instruction Formats

We are concerned with instruction length as well as instruction fields. In particular, for instruction fields, we are interested in the type and size of operands.

Instruction Length

1. Variable-Length Instructions

   • Examples:

     1. Intel 80x86: Instructions vary from 1 to 17 bytes long.
     2. Digital VAX: Instructions vary from 1 to 54 bytes long.

   • Require multi-step fetch and decode.

   • Allow for more flexible (but complex) and compact instruction set.

   

2. Fixed-Length Instructions

   • Examples:

     1. MIPS, PowerPC: Instructions are 4 bytes long.

   • Allow for easy fetch and decode.

   • Simplify pipelining and parallelism.
   • Instruction bits are scarce.

   

3. Hybrid Instructions: A mix of variable- and fixed-length instructions.

Instruction length is closely related to the encoding.

Instruction Fields

An instruction consists of:

1. Opcode: Unique code to specify the desired operation.
2. Operands: Zero or more additional information needed for the operation.

The operation designates the type and size of the operands. Typical type and size are as follows²:

• Characters: 8 bits.
• Half-Word: 16 bits.
• Word: 32 bits.
• Single-Precision Floating Point: 1 word.
• Double-Precision Floating Point: 2 words.

Given the typical size above, any new 32-bit architectures are expected to support 8-, 16- and 32-bit integer as well as 32- and 64-bit floating point operations. Additionally, a 64-bit architecture would need to support 64-bit integers as well.

Concept #5: Encoding the Instruction Set

Here, we are interested in how the instructions are represented in binary format for execution by the processor. This is the assembly process.

There are certain issues that we need to think about when we are designing the instruction set. Some of the common issues include the code size, speed (or performance) and design complexity. We further need to decide the following:

• Number of registers.
• Number of addressing modes.
• Number of operands in an instruction.

We generally have 3 encoding choices that are closely related to the instruction length.

Encoding

The fixed-length instruction presents a much more interesting challenge. We will need to fit multiple sets of instruction types into the same limited number of bits. To do that, we will need to work with the most constrained instruction types first. There is also the expanding opcode scheme that allows the opcode to have variable length for different instructions. We have encountered this before with the use of funct field. This is a good way to maximize the instruction bits.

Although there are some formula that can be used, the formula depends largely on the constraints that we have. As such, we will illustrate the encoding with examples instead.

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36 = opcode-bits + (2 × address-bits) + reg-number
36 = opcode-bits + (2 × 15          ) + 3
36 = opcode-bits + 33
3  = opcode-bits