

I am an assistant professor at the National University of Singapore working to develop high-efficiency microarchitectures that can meet the performance and needs of future IoT and server applications. To do this, we explore a number of computer-architecture related areas, from energy-efficient processors, to secure chips and neuromorphic accelerators. The foundation for our architecture research comes from our experience in fast and accurate simulation methodologies and analytical modeling. Additionally, I co-develop the Sniper Multi-Core Simulator.
If you are interested in conducting research into energy-efficient processors, secure computing platforms, neuromorphic accelerators, or simulation methodologies, contact us or see our open positions page for details.
Contact us at tcarlson<AT>comp.nus.edu.sg; You can find me at COM2-03-43.
[Google Scholar][ORCID][DBLP]
Work-in-progress
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Elasticlave: An Efficient Memory Model for Enclaves
Security
arXiv preprint arXiv:2010.08440, 2020.
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SOTERIA: In Search of Efficient Neural Networks for Private Inference
Artificial Intelligence
arXiv preprint arXiv:2007.12934, 2020.
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You Only Spike Once: Improving Energy-Efficient Neuromorphic Inference to ANN-Level Accuracy
Artificial Intelligence
arXiv preprint arXiv:2006.09982, 2020.
Selected Publications
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Laser Attack Benchmark Suite
Security Simulation
International Conference on Computer-Aided Design (ICCAD), 2020.
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Secure Your SoC: Building System-on-Chip Designs for Security
Security Simulation
International System-on-Chip Conference (SOCC), 2020.
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Directed Statistical Warming Through Time Traveling
Nominated Best Paper
Sampling Simulation
International Symposium on Microarchitecture (MICRO), 2019.
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Sampled Simulation of Task-Based Programs
Analytical Modeling Sampling
IEEE Transactions on Computers (TC), 2018.
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SWOOP: Software-Hardware Co-Design for Non-Speculative Execute-Ahead, In-Order Cores
Compilers Efficient Hardware
The ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), 2018.
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Non-Speculative Load Reordering in Total Store Ordering
Efficient Hardware
IEEE Micro Top Picks from the Computer Architecture Conferences (TopPicks), 2018.
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Maximizing Limited Resources: A Limit-Based Study and Taxonomy of Out-of-Order Commit
Performance Analysis Efficient Hardware
Journal of Signal Processing Systems, 2018.
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Behind the Scenes: Memory Analysis of Graphical Workloads on Tile-based GPUs
Nominated Best Paper
Performance Analysis
International Symposium on Performance Analysis of Systems and Software (ISPASS), 2018.
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Transcending Hardware Limits With Software Out-of-order Processing
Best of CAL
Efficient Hardware
International Symposium on High Performance Computer Architecture (HPCA), 2018.
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Static Instruction Scheduling for High Performance on Limited Hardware
Compilers
IEEE Transactions on Computers (TC), 2017.
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A Graphics Tracing Framework for Exploring CPU+GPU Memory Systems
Performance Analysis
IEEE International Symposium on Workload Characterization (IISWC), 2017.
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Non-Speculative Load-Load Reordering in TSO
Efficient Hardware
International Symposium on Computer Architecture (ISCA), 2017.
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Exploring the Performance Limits of Out-of-order Commit
Performance Analysis Efficient Hardware
Computing Frontiers Conference (CF), 2017.
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Clairvoyance: Look-ahead Compile-time Scheduling
Compilers
International Symposium on Code Generation and Optimization (CGO), 2017.
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Analytical Processor Performance and Power Modeling Using Micro-Architecture Independent Characteristics
Analytical Modeling
IEEE Transactions on Computers (TC), 2016.
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CoolSim: Statistical Techniques to Replace Cache Warming With Efficient, Virtualized Profiling
Best Paper
Simulation
Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), 2016.
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Long Term Parking (LTP): Criticality-aware Resource Allocation in OOO Processors
Efficient Hardware
International Symposium on Microarchitecture (MICRO), 2015.
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Full Speed Ahead: Detailed Architectural Simulation at Near-Native Speed
Simulation
IEEE International Symposium on Workload Characterization (IISWC), 2015.
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The Load Slice Core Microarchitecture
Efficient Hardware
International Symposium on Computer Architecture (ISCA), 2015.
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Chrysso: An Integrated Power Manager for Constrained Many-core Processors
Efficient Hardware
International Conference on Computing Frontiers (CF), 2015.
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Micro-architecture Independent Analytical Processor Performance and Power Modeling
Nominated Best Paper
Analytical Modeling
International Symposium on Performance Analysis of Systems and Software (ISPASS), 2015.
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An Evaluation of High-Level Mechanistic Core Models
Performance Analysis
Simulation
ACM Transactions on Architecture and Code Optimization (TACO), 2014.
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BarrierPoint: Sampled Simulation of Multi-threaded Applications
Nominated Best Paper
Sampling
International Symposium on Performance Analysis of Systems and Software (ISPASS), 2014.
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Undersubscribed Threading on Clustered Cache Architectures
Efficient Hardware
International Symposium on High Performance Computer Architecture (HPCA), 2014.
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PCantorSim: Accelerating Parallel Architecture Simulation Through Fractal-based Sampling
Sampling
ACM Transactions on Architecture and Code Optimization (TACO), 2013.
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Sampled Simulation of Multi-Threaded Applications
Best Paper
Sampling
International Symposium on Performance Analysis of Systems and Software (ISPASS), 2013.
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Power-Aware Multi-Core Simulation for Early Design Stage Hardware/Software Co-Optimization
Simulation
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT), 2012.
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Using Cycle Stacks to Understand Scaling Bottlenecks in Multi-threaded Workloads
Performance Analysis
IEEE International Symposium on Workload Characterization (IISWC), 2011.
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Sniper: Exploring the Level of Abstraction for Scalable and Accurate Parallel Multi-Core Simulations
Simulation
International Conference for High Performance Computing, Networking, Storage and Analysis (SC), 2011.
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Using Fast and Accurate Simulation to Explore Hardware/Software Trade-offs in the Multi-Core Era
Performance Analysis
International Conference on Parallel Computing (ParCo), 2011.
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3D Stacking of DRAM on Logic
Efficient Hardware
Three Dimensional System Integration: IC Stacking Process and Design, 2011.
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Automated Pathfinding Tool Chain for 3d-stacked Integrated Circuits: Practical Case Study
Performance Analysis
International Conference on 3D System Integration (3DIC), 2009.
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System-level Power/Performance Evaluation of 3D Stacked DRAMs for Mobile Applications
Performance Analysis
Efficient Hardware
Conference on Design, Automation and Test in Europe (DATE), 2009.
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Generic Multiphase Software Pipelined Partial FFT on Instruction Level Parallel Architectures
Efficient Hardware
IEEE Transactions on Signal Processing, 2009.