

I am an assistant professor at the National University of Singapore working to develop high-efficiency microarchitectures that can meet the performance and needs of future IoT and server applications. To do this, we explore a number of computer-architecture related areas, from energy-efficient processors, to secure chips and neuromorphic accelerators. The foundation for our architecture research comes from our experience in fast and accurate simulation methodologies and analytical modeling. Additionally, I co-develop the Sniper Multi-Core Simulator.
If you are interested in conducting research into energy-efficient processors, secure computing platforms, AI accelerators, programmable hardware, or simulation methodologies, contact us or see our open positions page for details.
[Google Scholar][ORCID][DBLP]; Contact us at tcarlson<AT>comp.nus.edu.sg; You can find me at COM3-2-10.
Navigate to Researchers, Code and Projects, Works-in-Progress, Publications
Researchers in our Lab
Postdocs | ||
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Ανδρέας Διαβαστός | Andreas Diavastos | Efficient Hardware Security |
PhD Students | ||
न्यूटन | Newton (with Virendra Singh) | Efficient Hardware |
บุรินทร์ อมรไพศาลนนท์ | Burin Amornpaisannon (with Li Shiuan Peh) | Artificial Intelligence Security |
陈韵 | Yun Chen | Efficient Hardware Security |
علی حاجی آبادی | Ali Hajiabadi | Efficient Hardware Security |
이진호 | Jinho Lee | Efficient Hardware |
刘常喜 | Changxi Liu | Simulation |
آرش پاش رشید | Arash Pashrashid | Security |
裴凌枫 | Lingfeng Pei | Efficient Hardware Security |
അലൻ കണ്ടത്തുംതൊടുകയിൽ സാബു | Alen Kandathumthodukayil Sabu | Simulation |
యశ్వంత్ తవ్వా | Yaswanth Tavva (with Li Shiuan Peh) | Security |
项婷婷 | Tingting Xiang | Artificial Intelligence |
于淼 | Miao Yu | Artificial Intelligence |
Researchers | ||
अर्चित अग्रवाल | Archit Agarwal | Security |
आकांक्षा चौधरी | Akanksha Chaudhari | Simulation |
උදාරී චතුරංගී හිරන්තිකා කනේවල | Udaree Kanewala | Efficient Hardware |
साई धवल फाये | Sai Dhawal Phaye | Security |
Undergraduate Researchers | ||
冯彦恺 | Yan Kai (Brandon) Foong | Security |
黄伟聪 | Weicong Huang | |
刘玮修 | Wei Siew Liew | Efficient Hardware |
刘志洋 | Zhiyang (Frank) Liu | Efficient Hardware |
刘骏 | Jun (Keith) Low | Efficient Hardware |
黄文丰 | Boon Hong Ng | |
王继寒 | Jihan Wang | Artificial Intelligence |
王宇辰 | Yuchen Wang | Simulation |
俞悦 | Yue Yu |
Code Repositories and Project Sites
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Fast, Robust and Accurate Detection of Cache-based Spectre Attack Phases
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Elasticlave: An Efficient Memory Model for Enclaves
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LoopPoint: Checkpoint-driven Sampled Simulation for Multi-threaded Applications
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ELFies: Executable Region Checkpoints for Performance Analysis and Simulation
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Laser Attack Benchmark Suite
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QAOAToolkit: Bringing Quantum Optimization to the End User
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Directed Statistical Warming Through Time Traveling
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An Evaluation of High-Level Mechanistic Core Models
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BarrierPoint: Sampled Simulation of Multi-threaded Applications
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Sniper: Exploring the Level of Abstraction for Scalable and Accurate Parallel Multi-Core Simulations
Works-in-progress
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Multiply-and-Fire (MNF): An Event-driven Sparse Neural Network Accelerator
Artificial Intelligence
arXiv preprint arXiv:2204.09797, 2022.
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Leaking Control Flow Information via the Hardware Prefetcher
Security
arXiv preprint arXiv:2109.00474, 2021.
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Mitigating Power Attacks Through Fine-Grained Instruction Reordering
Security
arXiv preprint arXiv:2107.11336, 2021.
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PIM-GraphSCC: PIM-Based Graph Processing Using Graph’s Community Structures
Efficient Hardware
Computer Architecture Letters (CAL), 2020.
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You Only Spike Once: Improving Energy-Efficient Neuromorphic Inference to ANN-Level Accuracy
Artificial Intelligence
arXiv preprint arXiv:2006.09982, 2020.
Selected Publications
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Fast, Robust and Accurate Detection of Cache-based Spectre Attack Phases
Security
International Conference on Computer-Aided Design (ICCAD), 2022.
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A Cross-Prefetcher Schedule Optimization Methodology
Efficient Hardware
IEEE Access, 2022.
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Efficient Instruction Scheduling Using Real-time Load Delay Tracking
Efficient Hardware
ACM Transactions on Computer Systems (TOCS), 2022.
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Elasticlave: An Efficient Memory Model for Enclaves
Security
USENIX Security Symposium, 2022.
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LoopPoint: Checkpoint-driven Sampled Simulation for Multi-threaded Applications
Simulation
International Symposium on High-Performance Computer Architecture (HPCA), 2022.
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GraphWave: A Highly-Parallel Compute-at-Memory Graph Processing Accelerator
Efficient Hardware
Design, Automation and Test in Europe Conference and Exhibition (DATE), 2022.
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Sentry-NoC: A Statically Scheduled NoC for Secure SoCs
Security
International Symposium on Networks-on-Chip (NOCS), 2021.
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Rectified Linear Postsynaptic Potential Function for Backpropagation in Deep Spiking Neural Networks
Artificial Intelligence
IEEE Transactions on Neural Networks and Learning Systems (TNNLS), 2021.
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Ultra-Fast CGRA Scheduling to Enable Run Time, Programmable CGRAs
Efficient Hardware
Design Automation Conference (DAC), 2021.
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Tatami: Dynamic CGRA Reconfiguration for Multi-Core General Purpose Processing
Efficient Hardware
Work-in-Progress at Design Automation Conference (DAC), 2021.
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NOREBA: A Compiler-Informed Non-speculative Out-of-Order Commit Processor
Efficient Hardware
Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2021.
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ELFies: Executable Region Checkpoints for Performance Analysis and Simulation
Performance Analysis Simulation
International Symposium on Code Generation and Optimization (CGO), 2021.
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SOTERIA: In Search of Efficient Neural Networks for Private Inference
Artificial Intelligence
arXiv preprint arXiv:2007.12934, 2020.
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A Framework for Developing Critical Literacies in Computer Architecture Education
International Conference on Teaching, Assessment, and Learning for Engineering (TALE), 2020.
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Laser Attack Benchmark Suite
Security Simulation
International Conference on Computer-Aided Design (ICCAD), 2020.
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QAOAToolkit: Bringing Quantum Optimization to the End User
Poster at International Workshop on Quantum Compilation (IWQC), 2020.
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Secure Your SoC: Building System-on-Chip Designs for Security
Security Simulation
International System-on-Chip Conference (SOCC), 2020.
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Directed Statistical Warming Through Time Traveling
Nominated Best Paper
Sampling Simulation
International Symposium on Microarchitecture (MICRO), 2019.
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Sampled Simulation of Task-Based Programs
Analytical Modeling Sampling
IEEE Transactions on Computers (TC), 2018.
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Active Learning to Develop Key Research Skills in Master’s Level Computer Science Coursework
International Conference on Teaching, Assessment, and Learning for Engineering (TALE), 2018.
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SWOOP: Software-Hardware Co-Design for Non-Speculative Execute-Ahead, In-Order Cores
Compilers Efficient Hardware
The ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), 2018.
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Non-Speculative Load Reordering in Total Store Ordering
Efficient Hardware
IEEE Micro Top Picks from the Computer Architecture Conferences (TopPicks), 2018.
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Maximizing Limited Resources: A Limit-Based Study and Taxonomy of Out-of-Order Commit
Performance Analysis Efficient Hardware
Journal of Signal Processing Systems, 2018.
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Power-performance Tradeoffs in Data Center Servers: DVFS, CPU Pinning, Horizontal, and Vertical Scaling
Performance Analysis
Future Generation Computer Systems, 2018.
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Behind the Scenes: Memory Analysis of Graphical Workloads on Tile-based GPUs
Nominated Best Paper
Performance Analysis
International Symposium on Performance Analysis of Systems and Software (ISPASS), 2018.
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Transcending Hardware Limits With Software Out-of-order Processing
Best of CAL
Efficient Hardware
International Symposium on High Performance Computer Architecture (HPCA), 2018.
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Static Instruction Scheduling for High Performance on Limited Hardware
Compilers
IEEE Transactions on Computers (TC), 2017.
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A Graphics Tracing Framework for Exploring CPU+GPU Memory Systems
Performance Analysis
IEEE International Symposium on Workload Characterization (IISWC), 2017.
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Non-Speculative Load-Load Reordering in TSO
Efficient Hardware
International Symposium on Computer Architecture (ISCA), 2017.
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Exploring the Performance Limits of Out-of-order Commit
Performance Analysis Efficient Hardware
Computing Frontiers Conference (CF), 2017.
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Clairvoyance: Look-ahead Compile-time Scheduling
Compilers
International Symposium on Code Generation and Optimization (CGO), 2017.
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Analytical Processor Performance and Power Modeling Using Micro-Architecture Independent Characteristics
Analytical Modeling
IEEE Transactions on Computers (TC), 2016.
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CoolSim: Statistical Techniques to Replace Cache Warming With Efficient, Virtualized Profiling
Best Paper
Simulation
Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), 2016.
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Long Term Parking (LTP): Criticality-aware Resource Allocation in OOO Processors
Efficient Hardware
International Symposium on Microarchitecture (MICRO), 2015.
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Full Speed Ahead: Detailed Architectural Simulation at Near-Native Speed
Simulation
IEEE International Symposium on Workload Characterization (IISWC), 2015.
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The Load Slice Core Microarchitecture
Efficient Hardware
International Symposium on Computer Architecture (ISCA), 2015.
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Chrysso: An Integrated Power Manager for Constrained Many-core Processors
Efficient Hardware
International Conference on Computing Frontiers (CF), 2015.
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Micro-architecture Independent Analytical Processor Performance and Power Modeling
Nominated Best Paper
Analytical Modeling
International Symposium on Performance Analysis of Systems and Software (ISPASS), 2015.
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An Evaluation of High-Level Mechanistic Core Models
Performance Analysis Simulation
ACM Transactions on Architecture and Code Optimization (TACO), 2014.
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BarrierPoint: Sampled Simulation of Multi-threaded Applications
Nominated Best Paper
Sampling
International Symposium on Performance Analysis of Systems and Software (ISPASS), 2014.
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Undersubscribed Threading on Clustered Cache Architectures
Efficient Hardware
International Symposium on High Performance Computer Architecture (HPCA), 2014.
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PCantorSim: Accelerating Parallel Architecture Simulation Through Fractal-based Sampling
Sampling
ACM Transactions on Architecture and Code Optimization (TACO), 2013.
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Sampled Simulation of Multi-Threaded Applications
Best Paper
Sampling
International Symposium on Performance Analysis of Systems and Software (ISPASS), 2013.
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Power-Aware Multi-Core Simulation for Early Design Stage Hardware/Software Co-Optimization
Simulation
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT), 2012.
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Using Cycle Stacks to Understand Scaling Bottlenecks in Multi-threaded Workloads
Performance Analysis
IEEE International Symposium on Workload Characterization (IISWC), 2011.
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Sniper: Exploring the Level of Abstraction for Scalable and Accurate Parallel Multi-Core Simulations
Simulation
International Conference for High Performance Computing, Networking, Storage and Analysis (SC), 2011.
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Using Fast and Accurate Simulation to Explore Hardware/Software Trade-offs in the Multi-Core Era
Performance Analysis
International Conference on Parallel Computing (ParCo), 2011.
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3D Stacking of DRAM on Logic
Efficient Hardware
Three Dimensional System Integration: IC Stacking Process and Design, 2011.
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Automated Pathfinding Tool Chain for 3d-stacked Integrated Circuits: Practical Case Study
Performance Analysis
International Conference on 3D System Integration (3DIC), 2009.
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System-level Power/Performance Evaluation of 3D Stacked DRAMs for Mobile Applications
Performance Analysis
Efficient Hardware
Conference on Design, Automation and Test in Europe (DATE), 2009.
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Generic Multiphase Software Pipelined Partial FFT on Instruction Level Parallel Architectures
Efficient Hardware
IEEE Transactions on Signal Processing, 2009.