I am an assistant professor at the National University of Singapore working to develop high-efficiency microarchitectures that can meet the performance and needs of future IoT and server applications. To do this, we explore a number of computer-architecture related areas, from energy-efficient processors, to secure chips and neuromorphic accelerators. The foundation for our architecture research comes from our experience in fast and accurate simulation methodologies and analytical modeling. Additionally, I co-develop the Sniper Multi-Core Simulator.
If you are interested in conducting research into energy-efficient processors, secure computing platforms, AI accelerators, programmable hardware, or simulation methodologies, contact us or see our open positions page for details.
[Google Scholar][ORCID][DBLP]; Contact us at tcarlson<AT>comp.nus.edu.sg; You can find me at COM3-02-10.
Navigate to Researchers, Alumni Researchers, Code and Projects, Works-in-Progress, Publications
Researchers in our Lab
PhD Students | ||
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บุรินทร์ อมรไพศาลนนท์ | Burin Amornpaisannon (with Li Shiuan Peh) | Artificial Intelligence Security |
付逸豪 | Yihao Fu | Security |
韩方祺 | Fangqi Han | Security |
උදාරී චතුරංගී හිරන්තිකා කනේවල | Udaree Kanewala | Efficient Hardware |
刘常喜 | Changxi Liu | Simulation |
آرش پاش رشید | Arash Pashrashid | Security |
裴凌枫 | Lingfeng Pei | Efficient Hardware Security |
അലൻ കണ്ടത്തുംതൊടുകയിൽ സാബു | Alen Kandathumthodukayil Sabu | Simulation |
యశ్వంత్ తవ్వా | Yaswanth Tavva (with Li Shiuan Peh) | Security |
项婷婷 | Tingting Xiang | Artificial Intelligence |
于淼 | Miao Yu | Artificial Intelligence |
Researchers | ||
साई धवल फाये | Sai Dhawal Phaye | Security |
Visiting Researchers | ||
Teodor-Ştefan Duțu | Teodor-Stefan Dutu | Efficient Hardware |
康清玄 | Qingxuan (Ray) Kang | Efficient Hardware Simulation |
刘畅 | Chang Liu | Security |
汪晓晨 | Xiaochen Wang | Efficient Hardware |
张鑫 | Xin Zhang | Security |
Undergraduate Researchers | ||
张钧勇 | Jin Yong (Kenny) Chon | Security |
이승섭 | Seoungsub Lee | Efficient Hardware |
张继堃 | Jikun Zhang | Artificial Intelligence Simulation |
Alumni Researchers
Postdocs | ||
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Ανδρέας Διαβαστός | Andreas Diavastos | Efficient Hardware Security |
వెంకట పవన్ కుమార్ మిరియాల | Venkata Pavan Kumar Miriyala | Artificial Intelligence |
खुशबू रानी | Khushboo Rani | Security |
PhD Students | ||
न्यूटन | Newton (with Virendra Singh) | Efficient Hardware |
陈韵 | Yun Chen | Efficient Hardware Security |
علی حاجی آبادی | Ali Hajiabadi | Efficient Hardware Security |
이진호 | Jinho Lee | Efficient Hardware |
Researchers | ||
अर्चित अग्रवाल | Archit Agarwal | Security |
आकांक्षा चौधरी | Akanksha Chaudhari | Simulation |
നീതു ബാൽ മല്ല്യ | Neethu Bal Mallya | |
Visiting Researchers | ||
مونا هاشمی | Mona Hashemi | Security |
Ionuț Mihalache | Ionut Mihalache | Efficient Hardware |
Undergraduate Researchers | ||
陈彤 | Tong Chen | Artificial Intelligence |
朱振忠 | Kyle Timothy Ng Chu | Artificial Intelligence Efficient Hardware |
范达熠 | Dayi Fan | |
冯彦恺 | Yan Kai (Brandon) Foong | Security |
黄伟聪 | Weicong Huang | |
康清玄 | Qingxuan (Ray) Kang | Simulation |
林俊宇 | Chun Yu Lam | Efficient Hardware |
刘玮修 | Wei Siew Liew | Efficient Hardware |
刘志洋 | Zhiyang (Frank) Liu | Efficient Hardware |
卢育全 | Keven Loo | Efficient Hardware |
刘骏 | Jun (Keith) Low | Efficient Hardware |
黄文丰 | Boon Hong Ng | |
Nguyễn Đăng Phúc Nhật | Dang Phuc Nhat Nguyen | |
Srivatsa P | ||
馮嘉俊 | Vernon Pang | |
陈界铭 | Kai Min (Russell) Tan | Efficient Hardware |
張偉政 | Wei Zheng Teo | |
王继寒 | Jihan Wang | Artificial Intelligence |
王宇辰 | Yuchen Wang | Simulation |
俞悦 | Yue Yu |
Code Repositories and Project Sites
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Prime+Reset: Introducing A Novel Cross-World Covert-Channel Through Comprehensive Security Analysis on ARM TrustZone
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PrefetchX: Cross-Core Cache-Agnostic Prefetcher-Based Side-Channel Attacks
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GadgetSpinner: A New Transient Execution Primitive using the Loop Stream Detector
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Photon: A Fine-grained Sampled Simulation Methodology for GPU Workloads
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Capstone: A Capability-based Foundation for Trustless Secure Memory Access
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AfterImage: Leaking Control Flow Data and Tracking Load Operations via the Hardware Prefetcher
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Fast, Robust and Accurate Detection of Cache-based Spectre Attack Phases
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Elasticlave: An Efficient Memory Model for Enclaves
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LoopPoint: Checkpoint-driven Sampled Simulation for Multi-threaded Applications
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ELFies: Executable Region Checkpoints for Performance Analysis and Simulation
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Laser Attack Benchmark Suite
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QAOAToolkit: Bringing Quantum Optimization to the End User
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Directed Statistical Warming Through Time Traveling
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Behind the Scenes: Memory Analysis of Graphical Workloads on Tile-based GPUs
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An Evaluation of High-Level Mechanistic Core Models
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BarrierPoint: Sampled Simulation of Multi-threaded Applications
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Sniper: Exploring the Level of Abstraction for Scalable and Accurate Parallel Multi-Core Simulations
Works-in-progress
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Providing High-Performance Execution with a Sequential Contract for Cryptographic Programs
arXiv preprint arXiv:2406.04290, 2024.
Security
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Fully Randomized Pointers
arXiv preprint arXiv:2405.12513, 2024.
Security
Selected Publications
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Mitigating Power Attacks Through Fine-Grained Instruction Reordering
ACM Transactions on Architecture and Code Optimization (TACO), 2024.
Security
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SRLL: Improving Security and Reliability With User-Defined Constraint-Aware Logic Locking
ACM Journal on Emerging Technologies in Computing Systems (JETC), 2024.
Security
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Pac-Sim: Simulation of Multi-threaded Workloads Using Intelligent, Live Sampling
ACM Transactions on Architecture and Code Optimization (TACO), 2024.
Sampling Simulation
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Improving (meta)comprehension: Feedback and Self-assessment
Journal of Learning and Instruction (JLI), 2024.
Education
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Conjuring: Leaking Control Flow via Speculative Fetch Attacks
Nominated Best Paper
Design Automation Conference (DAC), 2024.
Security
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Levioso: Efficient Compiler-Informed Secure Speculation
Design Automation Conference (DAC), 2024.
Security
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FAST-GO: Fast, Accurate, and Scalable Hardware Trojan Detection Using Graph Convolutional Networks
International Symposium on Quality Electronic Design (ISQED), 2024.
Security
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Prime+Reset: Introducing A Novel Cross-World Covert-Channel Through Comprehensive Security Analysis on ARM TrustZone
Design, Automation and Test in Europe Conference and Exhibition (DATE), 2024.
Security
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PrefetchX: Cross-Core Cache-Agnostic Prefetcher-Based Side-Channel Attacks
International Symposium on High-Performance Computer Architecture (HPCA), 2024.
Security
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GadgetSpinner: A New Transient Execution Primitive using the Loop Stream Detector
International Symposium on High-Performance Computer Architecture (HPCA), 2024.
Security
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Secure Run-Time Hardware Trojan Detection Using Lightweight Analytical Models
Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2024.
Analytical Modeling Security
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Viper: Utilizing Hierarchical Program Structure to Accelerate Multi-core Simulation
IEEE Access, 2024.
Sampling Simulation
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HidFix: Efficient Mitigation of Cache-based Spectre Attacks Through Hidden Rollbacks
International Conference on Computer-Aided Design (ICCAD), 2023.
Security
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Photon: A Fine-grained Sampled Simulation Methodology for GPU Workloads
International Symposium on Microarchitecture (MICRO), 2023.
Sampling Simulation
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Multiply-and-Fire: An Event-driven Sparse Neural Network Accelerator
ACM Transactions on Architecture and Code Optimization (TACO), 2023.
Artificial Intelligence
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3DRA: Dynamic Data-Driven Reconfigurable Architecture
IEEE Access, 2023.
Efficient Hardware
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Capstone: A Capability-based Foundation for Trustless Secure Memory Access
USENIX Security Symposium, 2023.
Security
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A TTFS-based Energy and Utilization Efficient Neuromorphic CNN Accelerator
Frontiers in Neuroscience, 2023.
Artificial Intelligence
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AfterImage: Leaking Control Flow Data and Tracking Load Operations via the Hardware Prefetcher
International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2023.
Security
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Fast, Robust and Accurate Detection of Cache-based Spectre Attack Phases
International Conference on Computer-Aided Design (ICCAD), 2022.
Security
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A Cross-Prefetcher Schedule Optimization Methodology
IEEE Access, 2022.
Efficient Hardware
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Efficient Instruction Scheduling Using Real-time Load Delay Tracking
ACM Transactions on Computer Systems (TOCS), 2022.
Efficient Hardware
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Elasticlave: An Efficient Memory Model for Enclaves
USENIX Security Symposium, 2022.
Security
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LoopPoint: Checkpoint-driven Sampled Simulation for Multi-threaded Applications
International Symposium on High-Performance Computer Architecture (HPCA), 2022.
Sampling Simulation
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GraphWave: A Highly-Parallel Compute-at-Memory Graph Processing Accelerator
Design, Automation and Test in Europe Conference and Exhibition (DATE), 2022.
Efficient Hardware
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Sentry-NoC: A Statically Scheduled NoC for Secure SoCs
International Symposium on Networks-on-Chip (NOCS), 2021.
Security
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Rectified Linear Postsynaptic Potential Function for Backpropagation in Deep Spiking Neural Networks
IEEE Transactions on Neural Networks and Learning Systems (TNNLS), 2021.
Artificial Intelligence
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Ultra-Fast CGRA Scheduling to Enable Run Time, Programmable CGRAs
Design Automation Conference (DAC), 2021.
Efficient Hardware
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Tatami: Dynamic CGRA Reconfiguration for Multi-Core General Purpose Processing
Work-in-Progress at Design Automation Conference (DAC), 2021.
Efficient Hardware
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NOREBA: A Compiler-Informed Non-speculative Out-of-Order Commit Processor
International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2021.
Efficient Hardware
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ELFies: Executable Region Checkpoints for Performance Analysis and Simulation
International Symposium on Code Generation and Optimization (CGO), 2021.
Performance Analysis Simulation
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SOTERIA: In Search of Efficient Neural Networks for Private Inference
arXiv preprint arXiv:2007.12934, 2020.
Artificial Intelligence
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A Framework for Developing Critical Literacies in Computer Architecture Education
International Conference on Teaching, Assessment, and Learning for Engineering (TALE), 2020.
Education
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Laser Attack Benchmark Suite
International Conference on Computer-Aided Design (ICCAD), 2020.
Security Simulation
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QAOAToolkit: Bringing Quantum Optimization to the End User
Poster at International Workshop on Quantum Compilation (IWQC), 2020.
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Secure Your SoC: Building System-on-Chip Designs for Security
International System-on-Chip Conference (SOCC), 2020.
Security Simulation
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PIM-GraphSCC: PIM-Based Graph Processing Using Graph’s Community Structures
Computer Architecture Letters (CAL), 2020.
Efficient Hardware
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Directed Statistical Warming Through Time Traveling
Nominated Best Paper
International Symposium on Microarchitecture (MICRO), 2019.
Sampling Simulation
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Sampled Simulation of Task-Based Programs
IEEE Transactions on Computers (TC), 2018.
Analytical Modeling Sampling
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Active Learning to Develop Key Research Skills in Master’s Level Computer Science Coursework
International Conference on Teaching, Assessment, and Learning for Engineering (TALE), 2018.
Education
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SWOOP: Software-Hardware Co-Design for Non-Speculative Execute-Ahead, In-Order Cores
The ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), 2018.
Compilers Efficient Hardware
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Non-Speculative Load Reordering in Total Store Ordering
IEEE Micro Top Picks from the Computer Architecture Conferences (TopPicks), 2018.
Efficient Hardware
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Maximizing Limited Resources: A Limit-Based Study and Taxonomy of Out-of-Order Commit
Journal of Signal Processing Systems, 2018.
Performance Analysis Efficient Hardware
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Power-performance Tradeoffs in Data Center Servers: DVFS, CPU Pinning, Horizontal, and Vertical Scaling
Future Generation Computer Systems, 2018.
Performance Analysis
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Behind the Scenes: Memory Analysis of Graphical Workloads on Tile-based GPUs
Nominated Best Paper
International Symposium on Performance Analysis of Systems and Software (ISPASS), 2018.
Performance Analysis
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Transcending Hardware Limits With Software Out-of-order Processing
Best of CAL
International Symposium on High Performance Computer Architecture (HPCA), 2018.
Efficient Hardware
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Static Instruction Scheduling for High Performance on Limited Hardware
IEEE Transactions on Computers (TC), 2017.
Compilers
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A Graphics Tracing Framework for Exploring CPU+GPU Memory Systems
IEEE International Symposium on Workload Characterization (IISWC), 2017.
Performance Analysis
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Non-Speculative Load-Load Reordering in TSO
International Symposium on Computer Architecture (ISCA), 2017.
Efficient Hardware
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Exploring the Performance Limits of Out-of-order Commit
Computing Frontiers Conference (CF), 2017.
Performance Analysis Efficient Hardware
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Clairvoyance: Look-ahead Compile-time Scheduling
International Symposium on Code Generation and Optimization (CGO), 2017.
Compilers
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Analytical Processor Performance and Power Modeling Using Micro-Architecture Independent Characteristics
IEEE Transactions on Computers (TC), 2016.
Analytical Modeling
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CoolSim: Statistical Techniques to Replace Cache Warming With Efficient, Virtualized Profiling
Best Paper
Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), 2016.
Simulation
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Long Term Parking (LTP): Criticality-aware Resource Allocation in OOO Processors
International Symposium on Microarchitecture (MICRO), 2015.
Efficient Hardware
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Full Speed Ahead: Detailed Architectural Simulation at Near-Native Speed
IEEE International Symposium on Workload Characterization (IISWC), 2015.
Simulation
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The Load Slice Core Microarchitecture
International Symposium on Computer Architecture (ISCA), 2015.
Efficient Hardware
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Epoch Profiles: Microarchitecture Application Analysis and Optimization
Computer Architecture Letters (CAL), 2015.
Performance Analysis
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Chrysso: An Integrated Power Manager for Constrained Many-core Processors
International Conference on Computing Frontiers (CF), 2015.
Efficient Hardware
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Micro-architecture Independent Analytical Processor Performance and Power Modeling
Nominated Best Paper
International Symposium on Performance Analysis of Systems and Software (ISPASS), 2015.
Analytical Modeling
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An Evaluation of High-Level Mechanistic Core Models
ACM Transactions on Architecture and Code Optimization (TACO), 2014.
Performance Analysis Simulation
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BarrierPoint: Sampled Simulation of Multi-threaded Applications
Nominated Best Paper
International Symposium on Performance Analysis of Systems and Software (ISPASS), 2014.
Sampling
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Undersubscribed Threading on Clustered Cache Architectures
International Symposium on High Performance Computer Architecture (HPCA), 2014.
Efficient Hardware
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PCantorSim: Accelerating Parallel Architecture Simulation Through Fractal-based Sampling
ACM Transactions on Architecture and Code Optimization (TACO), 2013.
Sampling
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Sampled Simulation of Multi-Threaded Applications
Best Paper
International Symposium on Performance Analysis of Systems and Software (ISPASS), 2013.
Sampling
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Power-Aware Multi-Core Simulation for Early Design Stage Hardware/Software Co-Optimization
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT), 2012.
Simulation
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Using Cycle Stacks to Understand Scaling Bottlenecks in Multi-threaded Workloads
IEEE International Symposium on Workload Characterization (IISWC), 2011.
Performance Analysis
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Sniper: Exploring the Level of Abstraction for Scalable and Accurate Parallel Multi-Core Simulations
International Conference for High Performance Computing, Networking, Storage and Analysis (SC), 2011.
Simulation
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Using Fast and Accurate Simulation to Explore Hardware/Software Trade-offs in the Multi-Core Era
International Conference on Parallel Computing (ParCo), 2011.
Performance Analysis
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3D Stacking of DRAM on Logic
Three Dimensional System Integration: IC Stacking Process and Design, 2011.
Efficient Hardware
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Automated Pathfinding Tool Chain for 3D-stacked Integrated Circuits: Practical Case Study
International Conference on 3D System Integration (3DIC), 2009.
Performance Analysis
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System-level Power/Performance Evaluation of 3D Stacked DRAMs for Mobile Applications
Conference on Design, Automation and Test in Europe (DATE), 2009.
Performance Analysis Efficient Hardware
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Generic Multiphase Software Pipelined Partial FFT on Instruction Level Parallel Architectures
IEEE Transactions on Signal Processing, 2009.
Efficient Hardware
* indicates equal contribution.