I am an assistant professor at the National University of Singapore working to develop high-efficiency microarchitectures that can meet the performance and needs of future IoT and server applications. To do this, we explore a number of computer-architecture related areas, from energy-efficient processors, to secure chips and neuromorphic accelerators. The foundation for our architecture research comes from our experience in fast and accurate simulation methodologies and analytical modeling. Additionally, I co-develop the Sniper Multi-Core Simulator.

If you are interested in conducting research into energy-efficient processors, secure computing platforms, neuromorphic accelerators, or simulation methodologies, contact us or see our open positions page for details.

Contact us at tcarlson<AT>comp.nus.edu.sg; You can find me at COM2-03-43.

[Google Scholar][ORCID][DBLP]

Work-in-progress

  1. Elasticlave: An Efficient Memory Model for Enclaves Security
    Z. Yu, S. Shinde, T. E. Carlson, and P. Saxena
    arXiv preprint arXiv:2010.08440, 2020.
  2. SOTERIA: In Search of Efficient Neural Networks for Private Inference Artificial Intelligence
    A. Aggarwal, T. E. Carlson, R. Shokri, and S. Tople
    arXiv preprint arXiv:2007.12934, 2020.
  3. You Only Spike Once: Improving Energy-Efficient Neuromorphic Inference to ANN-Level Accuracy Artificial Intelligence
    S. P, K. T. N. Chu, B. Amornpaisannon, Y. Tavva, V. Pavan Kumar Miriyala, J. Wu, M. Zhang, H. Li, and T. E. Carlson
    arXiv preprint arXiv:2006.09982, 2020.

Selected Publications

  1. Laser Attack Benchmark Suite Security Simulation
    B. Amornpaisannon, A. Diavastos, L.-S. Peh, and T. E. Carlson
    International Conference on Computer-Aided Design (ICCAD), 2020.
  2. Secure Your SoC: Building System-on-Chip Designs for Security Security Simulation
    S. Bhasin, T. E. Carlson, A. Chattopadhyay, V. B. Y. Kumar, A. Mendelson, R. Poussier, and Y. Tavva
    International System-on-Chip Conference (SOCC), 2020.
  3. Directed Statistical Warming Through Time Traveling Nominated Best Paper Sampling Simulation
    N. Nikoleris, L. Eeckhout, E. Hagersten, and T. E. Carlson
    International Symposium on Microarchitecture (MICRO), 2019.
  4. Sampled Simulation of Task-Based Programs Analytical Modeling Sampling
    T. Grass, T. E. Carlson, A. Rico, G. Ceballos, E. Ayguadé, M. Casas, and M. Moreto
    IEEE Transactions on Computers (TC), 2018.
  5. SWOOP: Software-Hardware Co-Design for Non-Speculative Execute-Ahead, In-Order Cores Compilers Efficient Hardware
    K.-A. Tran, A. Jimborean, T. E. Carlson, K. Koukos, M. Själander, and S. Kaxiras
    The ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), 2018.
  6. Non-Speculative Load Reordering in Total Store Ordering Efficient Hardware
    S. Kaxiras, T. E. Carlson, M. Alipour, and A. Ros
    IEEE Micro Top Picks from the Computer Architecture Conferences (TopPicks), 2018.
  7. Maximizing Limited Resources: A Limit-Based Study and Taxonomy of Out-of-Order Commit Performance Analysis Efficient Hardware
    M. Alipour, T. E. Carlson, D. Black-Schaffer, and S. Kaxiras
    Journal of Signal Processing Systems, 2018.
  8. Behind the Scenes: Memory Analysis of Graphical Workloads on Tile-based GPUs Nominated Best Paper Performance Analysis
    G. Ceballos, A. Sembrant, T. E. Carlson, and D. Black-Schaffer
    International Symposium on Performance Analysis of Systems and Software (ISPASS), 2018.
  9. Transcending Hardware Limits With Software Out-of-order Processing Best of CAL Efficient Hardware
    T. E. Carlson, K.-A. Tran, A. Jimborean, K. Koukos, M. Själander, and S. Kaxiras
    International Symposium on High Performance Computer Architecture (HPCA), 2018.
  10. Static Instruction Scheduling for High Performance on Limited Hardware Compilers
    K. A. Tran, T. E. Carlson, K. Koukos, M. Själander, V. Spiliopoulos, S. Kaxiras, and A. Jimborean
    IEEE Transactions on Computers (TC), 2017.
  11. A Graphics Tracing Framework for Exploring CPU+GPU Memory Systems Performance Analysis
    A. Sembrant, T. E. Carlson, E. Hagersten, and D. Black-Schaffer
    IEEE International Symposium on Workload Characterization (IISWC), 2017.
  12. Non-Speculative Load-Load Reordering in TSO Efficient Hardware
    A. Ros, T. E. Carlson, M. Alipour, and S. Kaxiras
    International Symposium on Computer Architecture (ISCA), 2017.
  13. Exploring the Performance Limits of Out-of-order Commit Performance Analysis Efficient Hardware
    M. Alipour, T. E. Carlson, and S. Kaxiras
    Computing Frontiers Conference (CF), 2017.
  14. Clairvoyance: Look-ahead Compile-time Scheduling Compilers
    K.-A. Tran, T. E. Carlson, K. Koukos, M. Själander, V. Spiliopoulos, S. Kaxiras, and A. Jimborean
    International Symposium on Code Generation and Optimization (CGO), 2017.
  15. Analytical Processor Performance and Power Modeling Using Micro-Architecture Independent Characteristics Analytical Modeling
    S. Van den Steen, S. Eyerman, S. D. Pestel, M. Mechri, T. E. Carlson, D. Black-Schaffer, E. Hagersten, and L. Eeckhout
    IEEE Transactions on Computers (TC), 2016.
  16. CoolSim: Statistical Techniques to Replace Cache Warming With Efficient, Virtualized Profiling Best Paper Simulation
    N. Nikoleris, A. Sandberg, E. Hagersten, and T. E. Carlson
    Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), 2016.
  17. Long Term Parking (LTP): Criticality-aware Resource Allocation in OOO Processors Efficient Hardware
    A. Sembrant, T. E. Carlson, E. Hagersten, D. Black-Shaffer, A. Perais, A. Seznec, and P. Michaud
    International Symposium on Microarchitecture (MICRO), 2015.
  18. Full Speed Ahead: Detailed Architectural Simulation at Near-Native Speed Simulation
    A. Sandberg, N. Nikoleris, T. E. Carlson, E. Hagersten, S. Kaxiras, and D. Black-Schaffer
    IEEE International Symposium on Workload Characterization (IISWC), 2015.
  19. The Load Slice Core Microarchitecture Efficient Hardware
    T. E. Carlson, W. Heirman, O. Allam, S. Kaxiras, and L. Eeckhout
    International Symposium on Computer Architecture (ISCA), 2015.
  20. Chrysso: An Integrated Power Manager for Constrained Many-core Processors Efficient Hardware
    S. S. Jha, W. Heirman, A. Falcón, T. E. Carlson, K. Van Craeynest, J. Tubella, A. González, and L. Eeckhout
    International Conference on Computing Frontiers (CF), 2015.
  21. Micro-architecture Independent Analytical Processor Performance and Power Modeling Nominated Best Paper Analytical Modeling
    S. Van den Steen, S. D. Pestel, M. Mechri, S. Eyerman, T. E. Carlson, D. Black-Schaffer, E. Hagersten, and L. Eeckhout
    International Symposium on Performance Analysis of Systems and Software (ISPASS), 2015.
  22. An Evaluation of High-Level Mechanistic Core Models Performance Analysis Simulation
    T. E. Carlson, W. Heirman, S. Eyerman, I. Hur, and L. Eeckhout
    ACM Transactions on Architecture and Code Optimization (TACO), 2014.
  23. BarrierPoint: Sampled Simulation of Multi-threaded Applications Nominated Best Paper Sampling
    T. E. Carlson, W. Heirman, K. V. Craeynest, and L. Eeckhout
    International Symposium on Performance Analysis of Systems and Software (ISPASS), 2014.
  24. Undersubscribed Threading on Clustered Cache Architectures Efficient Hardware
    W. Heirman, T. E. Carlson, K. Van Craeynest, I. Hur, A. Jaleel, and L. Eeckhout
    International Symposium on High Performance Computer Architecture (HPCA), 2014.
  25. PCantorSim: Accelerating Parallel Architecture Simulation Through Fractal-based Sampling Sampling
    C. Jiang, Z. Yu, H. Jin, C. Xu, L. Eeckhout, W. Heirman, T. E. Carlson, and X. Liao
    ACM Transactions on Architecture and Code Optimization (TACO), 2013.
  26. Sampled Simulation of Multi-Threaded Applications Best Paper Sampling
    T. E. Carlson, W. Heirman, and L. Eeckhout
    International Symposium on Performance Analysis of Systems and Software (ISPASS), 2013.
  27. Power-Aware Multi-Core Simulation for Early Design Stage Hardware/Software Co-Optimization Simulation
    W. Heirman, S. Sarkar, T. E. Carlson, I. Hur, and L. Eeckhout
    Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT), 2012.
  28. Using Cycle Stacks to Understand Scaling Bottlenecks in Multi-threaded Workloads Performance Analysis
    W. Heirman, T. E. Carlson, S. Che, K. Skadron, and L. Eeckhout
    IEEE International Symposium on Workload Characterization (IISWC), 2011.
  29. Sniper: Exploring the Level of Abstraction for Scalable and Accurate Parallel Multi-Core Simulations Simulation
    T. E. Carlson, W. Heirman, and L. Eeckhout
    International Conference for High Performance Computing, Networking, Storage and Analysis (SC), 2011.
  30. Using Fast and Accurate Simulation to Explore Hardware/Software Trade-offs in the Multi-Core Era Performance Analysis
    W. Heirman, T. E. Carlson, S. Sarkar, P. Ghysels, W. Vanroose, and L. Eeckhout
    International Conference on Parallel Computing (ParCo), 2011.
  31. 3D Stacking of DRAM on Logic Efficient Hardware
    T. E. Carlson and M. Facchini
    Three Dimensional System Integration: IC Stacking Process and Design, 2011.
  32. Automated Pathfinding Tool Chain for 3d-stacked Integrated Circuits: Practical Case Study Performance Analysis
    D. Milojevic, T. E. Carlson, K. Croes, R. Radojcic, D. F. Ragett, D. Seynhaeve, F. Angiolini, G. V. der Plas, and P. Marchal
    International Conference on 3D System Integration (3DIC), 2009.
  33. System-level Power/Performance Evaluation of 3D Stacked DRAMs for Mobile Applications Performance Analysis Efficient Hardware
    M. Facchini, T. E. Carlson, A. Vignon, M. Palkovic, F. Catthoor, W. Dehaene, L. Benini, and P. Marchal
    Conference on Design, Automation and Test in Europe (DATE), 2009.
  34. Generic Multiphase Software Pipelined Partial FFT on Instruction Level Parallel Architectures Efficient Hardware
    M. Li, D. Novo, B. Bougard, T. E. Carlson, L. V. D. Perre, and F. Catthoor
    IEEE Transactions on Signal Processing, 2009.