I am an associate professor in the Computer Science Department of the School of Computing at NUS. We work to build new hardware and software designs that improve the performance and security of computing systems, while still maintaining efficiency. The foundation for our architecture research comes from our experience and continued research in fast and accurate simulation methodologies and analytical modeling (See the Sniper Multi-Core Simulator for more details).

If you are interested in conducting research on secure computing platforms, AI accelerators, programmable hardware, or simulation methodologies, see our open positions page and application process and deadlines for details.

[Google Scholar][ORCID][DBLP]; Contact us at tcarlson<AT>nus.edu.sg; You can find me at COM3-02-10.

Navigate to Researchers, Alumni Researchers, Code and Projects, Works-in-Progress, Publications

Researchers in our Lab

Postdocs
บุรินทร์ อมรไพศาลนนท์ Burin Amornpaisannon Efficient Hardware Security
Gregory J. Duck Security
刘常喜 Changxi Liu Efficient Hardware Simulation
于淼 Miao Yu Artificial Intelligence Efficient Hardware
PhD Students
付逸豪 Yihao Fu systems
韩方祺 Fangqi Han PL and Compilers
උදාරී චතුරංගී හිරන්තිකා කනේවල Udaree Kanewala Efficient Hardware Security
康清玄 Qingxuan (Ray) Kang Efficient Hardware Simulation
이동인 Dongin Lee Simulation
马曦迪 Xidi Ma Artificial Intelligence Efficient Hardware
裴凌枫 Lingfeng Pei Efficient Hardware Security
యశ్వంత్ తవ్వా Yaswanth Tavva (with Li Shiuan Peh) Security
项婷婷 Tingting Xiang Artificial Intelligence Efficient Hardware
Visiting Researchers
程晓宇 Xiaoyu Cheng Security
朱冰 Bing Zhu Artificial Intelligence Efficient Hardware
Undergraduate Researchers
陈道恩 Dao En Ding PL and Compilers Efficient Hardware
何浩瑞 Haorui He Artificial Intelligence
林照锋 Jiu Fong Lam Artificial Intelligence Simulation
陈广哲 Kwang Thiag Tan Efficient Hardware
Ivan Tan Efficient Hardware
விஜயராகவன் விஷ்ணுபிரசாத் Vishnuprasath (Vishnu) Vijayaraghavan Artificial Intelligence Simulation
杨慧敏 Hui Min (Rachel) Yeo Artificial Intelligence
张皓翔 Haoxiang Zhang Artificial Intelligence Simulation

Alumni Researchers
Postdocs
Ανδρέας Διαβαστός Andreas Diavastos Efficient Hardware Security
مونا هاشمی Mona Hashemi Security
منصوره لباف نیا Mansoureh Labafniya Efficient Hardware Security
వెంకట పవన్ కుమార్ మిరియాల Venkata Pavan Kumar Miriyala Artificial Intelligence
खुशबू रानी Khushboo Rani Security
PhD Students
न्यूटन Newton (with Virendra Singh) Efficient Hardware
บุรินทร์ อมรไพศาลนนท์ Burin Amornpaisannon (with Li Shiuan Peh) Efficient Hardware Security
陈韵 Yun Chen Efficient Hardware Security
علی حاجی آبادی Ali Hajiabadi Efficient Hardware Security
이진호 Jinho Lee Efficient Hardware
刘常喜 Changxi Liu Efficient Hardware Simulation
آرش پاش رشید Arash Pashrashid Security
അലൻ കണ്ടത്തുംതൊടുകയിൽ സാബു Alen Kandathumthodukayil Sabu Simulation
于淼 Miao Yu Artificial Intelligence Efficient Hardware
Researchers
अर्चित अग्रवाल Archit Agarwal Security
आकांक्षा चौधरी Akanksha Chaudhari Simulation
നീതു ബാൽ മല്ല്യ Neethu Bal Mallya
साई धवल फाये Sai Dhawal Phaye Security
Visiting Researchers
Teodor-Ştefan Duțu Teodor-Stefan Dutu Efficient Hardware
مونا هاشمی Mona Hashemi Security
刘畅 Chang Liu Security
Ionuț Mihalache Ionut Mihalache Efficient Hardware
汪晓晨 Xiaochen Wang Efficient Hardware
张鑫 Xin Zhang Security
Undergraduate Researchers
陈彤 Tong Chen Artificial Intelligence
张钧勇 Jin Yong (Kenny) Chon Security
朱振忠 Kyle Timothy Ng Chu Artificial Intelligence Efficient Hardware
范达熠 Dayi Fan
冯彦恺 Yan Kai (Brandon) Foong Security
黄伟聪 Weicong Huang
康清玄 Qingxuan (Ray) Kang Simulation
林俊宇 Chun Yu Lam Efficient Hardware
刘玮修 Wei Siew Liew Efficient Hardware
刘志洋 Zhiyang (Frank) Liu Efficient Hardware
卢育全 Keven Loo Efficient Hardware
刘骏 Jun (Keith) Low Efficient Hardware
黄文丰 Boon Hong Ng
Nguyễn Đăng Phúc Nhật Dang Phuc Nhat Nguyen
Srivatsa P
馮嘉俊 Vernon Pang
陈界铭 Kai Min (Russell) Tan Efficient Hardware
張偉政 Wei Zheng Teo
王继寒 Jihan Wang Artificial Intelligence
王宇辰 Yuchen Wang Simulation
俞悦 Yue Yu
Liangqing Yuan systems
张继堃 Jikun Zhang Artificial Intelligence Simulation

Code Repositories and Project Sites
  1. Anvil: A General-Purpose Timing-Safe Hardware Description Language
  2. Accelerating the Simulation of Parallel Workloads Using Loop-Bounded Checkpoints
  3. SSBleed: Non-speculative Side-channel Attacks Via Speculative Store Bypass on Armv9 CPUs
  4. XPU-Point: Simulator-Agnostic Sample Selection Methodology for Heterogeneous CPU-GPU Applications
  5. Securing Mixed Rust with Hardware Capabilities
  6. Caplification: Bridging Capability-Aware and Capability-Oblivious Software
  7. Fully Randomized Pointers
  8. MDPeek: Breaking Balanced Branches in SGX With Memory Disambiguation Unit Side Channels
  9. Prime+Reset: Introducing A Novel Cross-World Covert-Channel Through Comprehensive Security Analysis on ARM TrustZone
  10. PrefetchX: Cross-Core Cache-Agnostic Prefetcher-Based Side-Channel Attacks
  11. GadgetSpinner: A New Transient Execution Primitive using the Loop Stream Detector
  12. Photon: A Fine-grained Sampled Simulation Methodology for GPU Workloads
  13. Capstone: A Capability-based Foundation for Trustless Secure Memory Access
  14. AfterImage: Leaking Control Flow Data and Tracking Load Operations via the Hardware Prefetcher
  15. Fast, Robust and Accurate Detection of Cache-based Spectre Attack Phases
  16. Elasticlave: An Efficient Memory Model for Enclaves
  17. LoopPoint: Checkpoint-driven Sampled Simulation for Multi-threaded Applications
  18. ELFies: Executable Region Checkpoints for Performance Analysis and Simulation
  19. Laser Attack Benchmark Suite
  20. QAOAToolkit: Bringing Quantum Optimization to the End User
  21. Directed Statistical Warming Through Time Traveling
  22. Behind the Scenes: Memory Analysis of Graphical Workloads on Tile-based GPUs
  23. An Evaluation of High-Level Mechanistic Core Models
  24. BarrierPoint: Sampled Simulation of Multi-threaded Applications
  25. Sniper: Exploring the Level of Abstraction for Scalable and Accurate Parallel Multi-Core Simulations

Works-in-progress
  1. Benchmarking for Single Feature Attribution with Microarchitecture Cliffs
    H. Zhen*, Q. Kang*, Y. Bao, and T. E. Carlson
    arXiv preprint arXiv:2602.11580, 2026.
    Simulation

Publications
  1. Silicon Valley’s Quiet Leak: Revealing User Activity on macOS for Apple Silicon
    X. Zhang, Z. Zhang, C. Liu, Q. Shen, and T. E. Carlson
    Black Hat Asia, 2026.
    Security
  2. Anvil: A General-Purpose Timing-Safe Hardware Description Language
    J. Z. Yu*, A. R. Jha*, U. Mathur, T. E. Carlson, and P. Saxena
    International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2026.
    PL and Compilers Efficient Hardware
  3. Accelerating the Simulation of Parallel Workloads Using Loop-Bounded Checkpoints
    A. Sabu, Z. Qui, H. Patil, C. Liu, W. Heirman, J. Lowe-Power, and T. E. Carlson
    ACM Transactions on Architecture and Code Optimization (TACO), 2026.
    Sampling Simulation
  4. SSBleed: Non-speculative Side-channel Attacks Via Speculative Store Bypass on Armv9 CPUs
    C. Liu, H. Zheng, X. Zhang, D. Ju, D. Wang, Y. Zhang, and T. E. Carlson
    International Symposium on High-Performance Computer Architecture (HPCA), 2026.
    Security
  5. XPU-Point: Simulator-Agnostic Sample Selection Methodology for Heterogeneous CPU-GPU Applications
    A. Sabu, H. Patil, W. Heirman, C. Liu, and T. E. Carlson
    Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT), 2025.
    Sampling
  6. Multi-Stream Squash Reuse for Control-Independent Processors
    Q. Kang and T. E. Carlson
    International Symposium on Microarchitecture (MICRO), 2025.
    Efficient Hardware
  7. Securing Mixed Rust with Hardware Capabilities
    J. Z. Yu*, F. Han*, K. Choudhury, T. E. Carlson, and P. Saxena
    Conference on Computer and Communications Security (CCS), 2025.
    Security
  8. Does Diagramming Improve Monitoring Accuracy of Intermediate-length and Long Texts?
    S. Hepner, S. Oudman, T. E. Carlson, M. McCrudden, and T. van Gog
    The European Association for Research on Learning and Instruction Conference (EARLI), 2025.
    Education
  9. TOP: A Combined Logical and Physical Obfuscation Method for Securing Networks-on-Chip Against Reverse Engineering Attacks
    M. Hashemi, S. Mohammadi, and T. E. Carlson
    IEEE Access, 2025.
    Security
  10. Caplification: Bridging Capability-Aware and Capability-Oblivious Software
    J. Z. Yu, M. Li, A. Badole, T. E. Carlson, M. Swift, and P. Saxena
    Symposium on Access Control Models and Technologies (SACMAT), 2025.
    Security
  11. Cassandra: Efficient Enforcement of Sequential Execution for Cryptographic Programs
    A. Hajiabadi and T. E. Carlson
    International Symposium on Computer Architecture (ISCA), 2025.
    Security
  12. The Sparsity-Aware LazyGPU Architecture
    C. Liu, M. Yu, Y. Sun, and T. E. Carlson
    International Symposium on Computer Architecture (ISCA), 2025.
    Efficient Hardware
  13. HoBBy: Hardening Unbalanced Branches against Control Flow Attacks on Intel SGX and AMD SEV
    C. Liu, S. Feng, Y. Li, D. Wang, and T. E. Carlson
    Design Automation Conference (DAC), 2025.
    Security
  14. SSFT: Algorithm and Hardware Co-design for Structured Sparse Fine-Tuning of Large Language Models
    M. Yu and T. E. Carlson
    Design Automation Conference (DAC), 2025.
    Artificial Intelligence Efficient Hardware
  15. LeakyDSP: Exploiting Digital Signal Processing Blocks to Sense Voltage Fluctuations in FPGAs
    X. Zhang, J. Zou, Y. Yang, Q. Shen, Z. Zhang, Y. Gao, Z. Wu, and T. E. Carlson
    Design Automation Conference (DAC), 2025.
    Security
  16. AmpereBleed: Exploiting On-chip Current Sensors for Circuit-Free Attacks on ARM-FPGA SoCs
    X. Zhang, Y. Yang, J. Zou, Q. Shen, Z. Zhang, Y. Gao, Z. Wu, and T. E. Carlson
    Design Automation Conference (DAC), 2025.
    Security
  17. Fully Randomized Pointers
    S. D. Phaye*, G. J. Duck*, R. H. C. Yap, and T. E. Carlson
    International Symposium on Memory Management (ISMM), 2025.
    Security
  18. MDPeek: Breaking Balanced Branches in SGX With Memory Disambiguation Unit Side Channels
    C. Liu, S. Feng, Y. Li, D. Wang, W. He, Y. Lyu, and T. E. Carlson
    International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2025.
    Security
  19. PARADISE: Criticality-Aware Instruction Reordering for Power Attack Resistance
    Y. Chen*, A. Hajiabadi*, R. Poussier, Y. Tavva, A. Diavastos, S. Bhasin, and T. E. Carlson
    ACM Transactions on Architecture and Code Optimization (TACO), 2025.
    Security
  20. CTScan: A CGRA-based Platform for the Emulation of Power Side-Channel Attacks on Edge CPUs
    Y. Tavva, R. Juneja, T. E. Carlson, and L. S. Peh
    ACM Transactions on Reconfigurable Technology and Systems (TRETS), 2025.
    Security
  21. Pac-Sim: Simulation of Multi-threaded Workloads Using Intelligent, Live Sampling
    C. Liu*, A. Sabu*, A. Chaudhari, Q. Kang, and T. E. Carlson
    ACM Transactions on Architecture and Code Optimization (TACO), 2024.
    Sampling Simulation
  22. Conjuring: Leaking Control Flow via Speculative Fetch Attacks Nominated Best Paper
    A. Hajiabadi and T. E. Carlson
    Design Automation Conference (DAC), 2024.
    Security
  23. Levioso: Efficient Compiler-Informed Secure Speculation
    A. Hajiabadi, A. Agarwal, A. Diavastos, and T. E. Carlson
    Design Automation Conference (DAC), 2024.
    Security
  24. Improving (meta)comprehension: Feedback and Self-assessment
    S. L. Hepner, S. Oudman, T. E. Carlson, J. van de Pol, and T. van Gog
    Journal of Learning and Instruction (JLI), 2024.
    Education
  25. FAST-GO: Fast, Accurate, and Scalable Hardware Trojan Detection Using Graph Convolutional Networks
    A. Imangholi*, M. Hashemi*, A. Momeni, S. Mohammadi, and T. E. Carlson
    International Symposium on Quality Electronic Design (ISQED), 2024.
    Security
  26. ×
    Prime+Reset: Introducing A Novel Cross-World Covert-Channel Through Comprehensive Security Analysis on ARM TrustZone
    Y. Chen*, A. Pashrashid*, Y. Wu, and T. E. Carlson
    Design, Automation and Test in Europe Conference and Exhibition (DATE), 2024.
    Security
  27. PrefetchX: Cross-Core Cache-Agnostic Prefetcher-Based Side-Channel Attacks
    Y. Chen, A. Hajiabadi, L. Pei, and T. E. Carlson
    International Symposium on High-Performance Computer Architecture (HPCA), 2024.
    Security
  28. GadgetSpinner: A New Transient Execution Primitive using the Loop Stream Detector
    Y. Chen*, A. Hajiabadi*, and T. E. Carlson
    International Symposium on High-Performance Computer Architecture (HPCA), 2024.
    Security
  29. Secure Run-Time Hardware Trojan Detection Using Lightweight Analytical Models
    B. Amornpaisannon, A. Diavastos, L.-S. Peh, and T. E. Carlson
    Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2024.
    Analytical Modeling Security
  30. Viper: Utilizing Hierarchical Program Structure to Accelerate Multi-core Simulation
    A. Sabu*, C. Liu*, and T. E. Carlson
    IEEE Access, 2024.
    Sampling Simulation
  31. SRLL: Improving Security and Reliability With User-Defined Constraint-Aware Logic Locking
    M. Hashemi, S. Mohammadi, and T. E. Carlson
    ACM Journal on Emerging Technologies in Computing Systems (JETC), 2024.
    Security
  32. HidFix: Efficient Mitigation of Cache-based Spectre Attacks Through Hidden Rollbacks
    A. Pashrashid, A. Hajiabadi, and T. E. Carlson
    International Conference on Computer-Aided Design (ICCAD), 2023.
    Security
  33. Photon: A Fine-grained Sampled Simulation Methodology for GPU Workloads
    C. Liu, Y. Sun, and T. E. Carlson
    International Symposium on Microarchitecture (MICRO), 2023.
    Sampling Simulation
  34. Multiply-and-Fire: An Event-driven Sparse Neural Network Accelerator
    M. Yu*, T. Xiang*, V. P. K. Miriyala, and T. E. Carlson
    ACM Transactions on Architecture and Code Optimization (TACO), 2023.
    Artificial Intelligence
  35. 3DRA: Dynamic Data-Driven Reconfigurable Architecture
    J. Lee, B. Amornpaisannon, A. Diavastos, and T. E. Carlson
    IEEE Access, 2023.
    Efficient Hardware
  36. Capstone: A Capability-based Foundation for Trustless Secure Memory Access
    J. Z. Yu, C. Watt, A. Badole, T. E. Carlson, and P. Saxena
    USENIX Security Symposium, 2023.
    Security
  37. A TTFS-based Energy and Utilization Efficient Neuromorphic CNN Accelerator
    M. Yu, T. Xiang, S. P., K. T. N. Chu, B. Amornpaisannon, Y. Tavva, V. P. K. Miriyala, and T. E. Carlson
    Frontiers in Neuroscience, 2023.
    Artificial Intelligence
  38. AfterImage: Leaking Control Flow Data and Tracking Load Operations via the Hardware Prefetcher
    Y. Chen, L. Pei, and T. E. Carlson
    International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2023.
    Security
  39. Efficient Instruction Scheduling Using Real-time Load Delay Tracking
    A. Diavastos and T. E. Carlson
    ACM Transactions on Computer Systems (TOCS), 2022.
    Efficient Hardware
  40. ×
    Fast, Robust and Accurate Detection of Cache-based Spectre Attack Phases
    A. Pashrashid, A. Hajiabadi, and T. E. Carlson
    International Conference on Computer-Aided Design (ICCAD), 2022.
    Security
  41. ×
    Elasticlave: An Efficient Memory Model for Enclaves
    Z. Yu, S. Shinde, T. E. Carlson, and P. Saxena
    USENIX Security Symposium, 2022.
    Security
  42. A Cross-Prefetcher Schedule Optimization Methodology
    R. Niţu, L. Pei, and T. E. Carlson
    IEEE Access, 2022.
    Efficient Hardware
  43. LoopPoint: Checkpoint-driven Sampled Simulation for Multi-threaded Applications
    A. Sabu, H. Patil, W. Heirman, and T. E. Carlson
    International Symposium on High-Performance Computer Architecture (HPCA), 2022.
    Sampling Simulation
  44. ×
    GraphWave: A Highly-Parallel Compute-at-Memory Graph Processing Accelerator
    J. Lee*, B. Amornpaisannon*, T. Mitra, and T. E. Carlson
    Design, Automation and Test in Europe Conference and Exhibition (DATE), 2022.
    Efficient Hardware
  45. Sentry-NoC: A Statically Scheduled NoC for Secure SoCs
    A. Shalaby, Y. Tavva, T. E. Carlson, and L.-S. Peh
    International Symposium on Networks-on-Chip (NOCS), 2021.
    Security
  46. Rectified Linear Postsynaptic Potential Function for Backpropagation in Deep Spiking Neural Networks
    M. Zhang, J. Wang, J. Wu, A. Belatreche, B. Amornpaisannon, Z. Zhang, V. P. K. Miriyala, H. Qu, Y. Chua, T. E. Carlson, and H. Li
    IEEE Transactions on Neural Networks and Learning Systems (TNNLS), 2021.
    Artificial Intelligence
  47. ×
    Ultra-Fast CGRA Scheduling to Enable Run Time, Programmable CGRAs
    J. Lee and T. E. Carlson
    Design Automation Conference (DAC), 2021.
    Efficient Hardware
  48. Tatami: Dynamic CGRA Reconfiguration for Multi-Core General Purpose Processing
    J. Lee and T. E. Carlson
    Work-in-Progress at Design Automation Conference (DAC), 2021.
    Efficient Hardware
  49. NOREBA: A Compiler-Informed Non-speculative Out-of-Order Commit Processor
    A. Hajiabadi, A. Diavastos, and T. E. Carlson
    International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2021.
    Efficient Hardware
  50. ELFies: Executable Region Checkpoints for Performance Analysis and Simulation
    H. Patil, A. Isaev, W. Heirman, A. Sabu, A. Hajiabadi, and T. E. Carlson
    International Symposium on Code Generation and Optimization (CGO), 2021.
    Performance Analysis Simulation
  51. A Framework for Developing Critical Literacies in Computer Architecture Education
    S. L. Hepner and T. E. Carlson
    International Conference on Teaching, Assessment, and Learning for Engineering (TALE), 2020.
    Education
  52. ×
    Laser Attack Benchmark Suite
    B. Amornpaisannon, A. Diavastos, L.-S. Peh, and T. E. Carlson
    International Conference on Computer-Aided Design (ICCAD), 2020.
    Security Simulation
  53. QAOAToolkit: Bringing Quantum Optimization to the End User
    T. Anandakkoomar, P. Rebentrost, and T. E. Carlson
    Poster at International Workshop on Quantum Compilation (IWQC), 2020.
    PL and Compilers
  54. Secure Your SoC: Building System-on-Chip Designs for Security
    S. Bhasin, T. E. Carlson, A. Chattopadhyay, V. B. Y. Kumar, A. Mendelson, R. Poussier, and Y. Tavva
    International System-on-Chip Conference (SOCC), 2020.
    Security Simulation
  55. SOTERIA: In Search of Efficient Neural Networks for Private Inference
    A. Aggarwal, T. E. Carlson, R. Shokri, and S. Tople
    arXiv preprint arXiv:2007.12934, 2020.
    Artificial Intelligence
  56. PIM-GraphSCC: PIM-Based Graph Processing Using Graph’s Community Structures
    Newton, V. Singh, and T. E. Carlson
    Computer Architecture Letters (CAL), 2020.
    Efficient Hardware
  57. Directed Statistical Warming Through Time Traveling Nominated Best Paper
    N. Nikoleris, L. Eeckhout, E. Hagersten, and T. E. Carlson
    International Symposium on Microarchitecture (MICRO), 2019.
    Sampling Simulation
  58. Active Learning to Develop Key Research Skills in Master’s Level Computer Science Coursework
    S. L. Hepner and T. E. Carlson
    International Conference on Teaching, Assessment, and Learning for Engineering (TALE), 2018.
    Education
  59. Sampled Simulation of Task-Based Programs
    T. Grass, T. E. Carlson, A. Rico, G. Ceballos, E. Ayguadé, M. Casas, and M. Moreto
    IEEE Transactions on Computers (TC), 2018.
    Analytical Modeling Sampling
  60. SWOOP: Software-Hardware Co-Design for Non-Speculative Execute-Ahead, In-Order Cores
    K.-A. Tran, A. Jimborean, T. E. Carlson, K. Koukos, M. Själander, and S. Kaxiras
    The ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), 2018.
    PL and Compilers Efficient Hardware
  61. Non-Speculative Load Reordering in Total Store Ordering
    S. Kaxiras, T. E. Carlson, M. Alipour, and A. Ros
    IEEE Micro Top Picks from the Computer Architecture Conferences (TopPicks), 2018.
    Efficient Hardware
  62. Maximizing Limited Resources: A Limit-Based Study and Taxonomy of Out-of-Order Commit
    M. Alipour, T. E. Carlson, D. Black-Schaffer, and S. Kaxiras
    Journal of Signal Processing Systems, 2018.
    Performance Analysis Efficient Hardware
  63. Power-performance Tradeoffs in Data Center Servers: DVFS, CPU Pinning, Horizontal, and Vertical Scaling
    J. Krzywda, A. Ali-Eldin, T. E. Carlson, P.-O. Östberg, and E. Elmroth
    Future Generation Computer Systems, 2018.
    Performance Analysis
  64. Behind the Scenes: Memory Analysis of Graphical Workloads on Tile-based GPUs Nominated Best Paper
    G. Ceballos, A. Sembrant, T. E. Carlson, and D. Black-Schaffer
    International Symposium on Performance Analysis of Systems and Software (ISPASS), 2018.
    Performance Analysis
  65. Transcending Hardware Limits With Software Out-of-order Processing Best of CAL
    T. E. Carlson, K.-A. Tran, A. Jimborean, K. Koukos, M. Själander, and S. Kaxiras
    International Symposium on High Performance Computer Architecture (HPCA), 2018.
    Efficient Hardware
  66. Static Instruction Scheduling for High Performance on Limited Hardware
    K. A. Tran, T. E. Carlson, K. Koukos, M. Själander, V. Spiliopoulos, S. Kaxiras, and A. Jimborean
    IEEE Transactions on Computers (TC), 2017.
    PL and Compilers
  67. A Graphics Tracing Framework for Exploring CPU+GPU Memory Systems
    A. Sembrant, T. E. Carlson, E. Hagersten, and D. Black-Schaffer
    IEEE International Symposium on Workload Characterization (IISWC), 2017.
    Performance Analysis
  68. Non-Speculative Load-Load Reordering in TSO
    A. Ros, T. E. Carlson, M. Alipour, and S. Kaxiras
    International Symposium on Computer Architecture (ISCA), 2017.
    Efficient Hardware
  69. Exploring the Performance Limits of Out-of-order Commit
    M. Alipour, T. E. Carlson, and S. Kaxiras
    Computing Frontiers Conference (CF), 2017.
    Performance Analysis Efficient Hardware
  70. Clairvoyance: Look-ahead Compile-time Scheduling
    K.-A. Tran, T. E. Carlson, K. Koukos, M. Själander, V. Spiliopoulos, S. Kaxiras, and A. Jimborean
    International Symposium on Code Generation and Optimization (CGO), 2017.
    PL and Compilers
  71. Analytical Processor Performance and Power Modeling Using Micro-Architecture Independent Characteristics
    S. Van den Steen, S. Eyerman, S. D. Pestel, M. Mechri, T. E. Carlson, D. Black-Schaffer, E. Hagersten, and L. Eeckhout
    IEEE Transactions on Computers (TC), 2016.
    Analytical Modeling
  72. CoolSim: Statistical Techniques to Replace Cache Warming With Efficient, Virtualized Profiling Best Paper
    N. Nikoleris, A. Sandberg, E. Hagersten, and T. E. Carlson
    Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), 2016.
    Simulation
  73. Full Speed Ahead: Detailed Architectural Simulation at Near-Native Speed
    A. Sandberg, N. Nikoleris, T. E. Carlson, E. Hagersten, S. Kaxiras, and D. Black-Schaffer
    IEEE International Symposium on Workload Characterization (IISWC), 2015.
    Simulation
  74. Epoch Profiles: Microarchitecture Application Analysis and Optimization
    T. E. Carlson, S. Nilakantan, M. Hempstead, and W. Heirman
    Computer Architecture Letters (CAL), 2015.
    Performance Analysis
  75. The Load Slice Core Microarchitecture
    T. E. Carlson, W. Heirman, O. Allam, S. Kaxiras, and L. Eeckhout
    International Symposium on Computer Architecture (ISCA), 2015.
    Efficient Hardware
  76. Micro-architecture Independent Analytical Processor Performance and Power Modeling Nominated Best Paper
    S. Van den Steen, S. D. Pestel, M. Mechri, S. Eyerman, T. E. Carlson, D. Black-Schaffer, E. Hagersten, and L. Eeckhout
    International Symposium on Performance Analysis of Systems and Software (ISPASS), 2015.
    Analytical Modeling
  77. Long Term Parking (LTP): Criticality-aware Resource Allocation in OOO Processors
    A. Sembrant, T. E. Carlson, E. Hagersten, D. Black-Shaffer, A. Perais, A. Seznec, and P. Michaud
    International Symposium on Microarchitecture (MICRO), 2015.
    Efficient Hardware
  78. Chrysso: An Integrated Power Manager for Constrained Many-core Processors
    S. S. Jha, W. Heirman, A. Falcón, T. E. Carlson, K. Van Craeynest, J. Tubella, A. González, and L. Eeckhout
    International Conference on Computing Frontiers (CF), 2015.
    Efficient Hardware
  79. An Evaluation of High-Level Mechanistic Core Models
    T. E. Carlson, W. Heirman, S. Eyerman, I. Hur, and L. Eeckhout
    ACM Transactions on Architecture and Code Optimization (TACO), 2014.
    Performance Analysis Simulation
  80. BarrierPoint: Sampled Simulation of Multi-threaded Applications Nominated Best Paper
    T. E. Carlson, W. Heirman, K. V. Craeynest, and L. Eeckhout
    International Symposium on Performance Analysis of Systems and Software (ISPASS), 2014.
    Sampling
  81. Undersubscribed Threading on Clustered Cache Architectures
    W. Heirman, T. E. Carlson, K. Van Craeynest, I. Hur, A. Jaleel, and L. Eeckhout
    International Symposium on High Performance Computer Architecture (HPCA), 2014.
    Efficient Hardware
  82. PCantorSim: Accelerating Parallel Architecture Simulation Through Fractal-based Sampling
    C. Jiang, Z. Yu, H. Jin, C. Xu, L. Eeckhout, W. Heirman, T. E. Carlson, and X. Liao
    ACM Transactions on Architecture and Code Optimization (TACO), 2013.
    Sampling
  83. Sampled Simulation of Multi-Threaded Applications Best Paper
    T. E. Carlson, W. Heirman, and L. Eeckhout
    International Symposium on Performance Analysis of Systems and Software (ISPASS), 2013.
    Sampling
  84. Power-Aware Multi-Core Simulation for Early Design Stage Hardware/Software Co-Optimization
    W. Heirman, S. Sarkar, T. E. Carlson, I. Hur, and L. Eeckhout
    Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT), 2012.
    Simulation
  85. Using Cycle Stacks to Understand Scaling Bottlenecks in Multi-threaded Workloads
    W. Heirman, T. E. Carlson, S. Che, K. Skadron, and L. Eeckhout
    IEEE International Symposium on Workload Characterization (IISWC), 2011.
    Performance Analysis
  86. Sniper: Exploring the Level of Abstraction for Scalable and Accurate Parallel Multi-Core Simulations
    T. E. Carlson, W. Heirman, and L. Eeckhout
    International Conference for High Performance Computing, Networking, Storage and Analysis (SC), 2011.
    Simulation
  87. Using Fast and Accurate Simulation to Explore Hardware/Software Trade-offs in the Multi-Core Era
    W. Heirman, T. E. Carlson, S. Sarkar, P. Ghysels, W. Vanroose, and L. Eeckhout
    International Conference on Parallel Computing (ParCo), 2011.
    Performance Analysis
  88. 3D Stacking of DRAM on Logic
    T. E. Carlson and M. Facchini
    Three Dimensional System Integration: IC Stacking Process and Design, 2011.
    Efficient Hardware
  89. Automated Pathfinding Tool Chain for 3D-stacked Integrated Circuits: Practical Case Study
    D. Milojevic, T. E. Carlson, K. Croes, R. Radojcic, D. F. Ragett, D. Seynhaeve, F. Angiolini, G. V. der Plas, and P. Marchal
    International Conference on 3D System Integration (3DIC), 2009.
    Performance Analysis
  90. System-level Power/Performance Evaluation of 3D Stacked DRAMs for Mobile Applications
    M. Facchini, T. E. Carlson, A. Vignon, M. Palkovic, F. Catthoor, W. Dehaene, L. Benini, and P. Marchal
    Conference on Design, Automation and Test in Europe (DATE), 2009.
    Performance Analysis Efficient Hardware
  91. Generic Multiphase Software Pipelined Partial FFT on Instruction Level Parallel Architectures
    M. Li, D. Novo, B. Bougard, T. E. Carlson, L. V. D. Perre, and F. Catthoor
    IEEE Transactions on Signal Processing, 2009.
    Efficient Hardware


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